论文信息 - High efficient 3-input XOR for low-voltage low-power high-speed applications

High efficient 3-input XOR for low-voltage low-power high-speed applications

A new 3-input XOR gate based upon the pass transistor design methodology for low-voltage, low-voltage high-speed applications is proposed. Five existing circuits are compared with the new proposed gate. It is shown that the proposed new circuit has at least 50% improvement in power-delay product than that of the CPL structure and the CMOS structure. Moreover, the proposed new circuit can also be operated as low as 1 V. Thus, the proposed new circuit is suitable for low-power, low-voltage and high-speed applications.

Kuo-Hsing Cheng | Ven-Chieh Hsieh

[1] Makoto Suzuki,et al. A 1.5-ns 32-b CMOS ALU in double pass-transistor logic , 1993 .

[2] Haomin Wu,et al. A new design of the CMOS full adder , 1992 .

[3] Wolfgang Fichtner,et al. Low-power logic styles: CMOS versus pass-transistor logic , 1997, IEEE J. Solid State Circuits.

[4] Wu-Shiung Feng,et al. A new direct design for three-input XOR function on the transistor level , 1996 .

[5] Kazuo Yano,et al. A 3.8-ns CMOS 16*16-b multiplier using complementary pass-transistor logic , 1990 .