Topics in IC Layout for Manufacture

By the end of the circuit-design phase of an IC product of even modest complexity, many hundreds, and often thousands, of decisions will have been considered and weighed, and the basic “electrical” compromises and trade-offs will have been settled. However, the product development still has a long way to go. The next step – the preparation of a set of layout drawings – is always crucial to a successful implementation, but particularly so where there is a substantial amount of analog circuitry. This distinction arises partly from the fact that analog cells and architectures are sensitive to numerous tiny details, which makes the transition from schematic to an intelligent layout a far more demanding exercise. Cell reuse is an appealing idea, both at the circuit development stage and particularly in layout, where verbatim copying, using “cut-and-paste”, can save a great deal of time. In practice, however, it is hard to implement this approach in the analog domain, where each system poses subtle differences in the signal environment and performance objectives. Analog layout for new products is invariably forced to be “hand-crafted”. This is true even when using some sort of auto-routing software, which is not yet smart enough to do a satisfactory job. By contrast, digital systems-on-a-chip (SoCs) must – and routinely do – take advantage of reuse, whether of proven transistor-level cells, logical processing algorithms, functional blocks, or even of large areas of the layout, with relatively minor modifications. But here too, this general rule takes on a different aspect when the leap is made to a much denser process, requiring the generation of a new family of logic cells, or when data and clock rates are increased by large factors, requiring a more thorough “physics-based” consideration of signal propagation along the interconnects, which must now be viewed as transmission lines and analyzed using electromagnetic theory. Current predictions about CPU clock rates reaching 20 GHz by 2009 using 30-nm gate-length transistors raise an entirely new set of questions in this regard. Analog design skills and layout expertise will be much in demand for the all-digital SoC’s of the future. Nevertheless, the fact remains that the function of even large clusters of binary cells is basically simple and their response to a set of input states is