Area/yield trade-offs in scaled CMOS SRAM cell

A statistical design method, for the SRAM bit-cell, is proposed to ensure a high yield, while meeting the specifications of stability, writability, read speed, leakage and area. Optimal bit-cell designs in the 65 nm, 45 nm and 32 nm technologies are derived. It is demonstrated that memory partitioning and longer transistors enable smaller transistor widths, and a close to 50% scaling of the bit-cell area with technology.

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