Design of dual-port video buffer based on FPGA

The design of dual-port video buffer based on FPGA and SDRAM is introduced.The user interfaces are composed of small capacity synchronous FIFO and asynchronous FIFO in series connection.The SDRAM is accessed in burst mode.The arbitrator uses a modified algorithm to grant the right to use the bus of SDRAM.The single memory can store the captured data and provide data for displaying simultaneously.Experimental results indicate when SDRAM works in 71 MHz,there are no error in the video data transmission.This system is simple and easy to be debugged.By changing relevant parameters of FIFOs and length of the block,the actual bandwidth of SDRAM can achieve a high performance.