Hardware Implementation of Autoregressive Model Estimation Using Burg’s Method for Low-Energy Spectral Analysis

We present a hardware implementation of Burg’s method, which is used for autoregressive (AR) model estimation. The AR model is a linear predictive modeling technique. It assumes that the current value of a signal can be described by a finite linear aggregate of the previous values. The AR model can be used for spectral analysis as an alternative to the Fourier transform. This approach is a parametric method, and it can yield higher resolutions than nonparametric methods in cases when the signal length is short. Although Burg’s method requires a large computational capacity, especially with higher model orders, a fast Burg’s method has been proposed for improving this drawback. In this study, we evaluate the influence of the order and the data length of Burg’s method on the computational capacity. The hardware implementation method of the fast Burg’s method including a two-stage pipeline architecture and a parallelization technique for autocorrelation calculations is proposed. The proposed method is implemented using Verilog HDL and its energy consumption is estimated with the 65-nm CMOS process. The evaluation result shows that the proposed method achieves an energy consumption of 21.6–361.4 nJ for the spectral estimation with a data length of 128–2048 points when the model order is 5.