Techniques for low power realization of FIR filters

We propose techniques for low power realization of FIR filters on programmable DSPs. We first analyse the FIR implementation to arrive at useful measures to reduce power and present techniques that exploit these measures. We then identify limitations of the existing DSP architectures in implementing these techniques and propose simple architectural extensions to overcome these limitations. Finally we present experimental results on real FIR filter examples that show up to 88% reduction in coefficient memory data bus power, upto 49% reduction in coefficient memory address bus power.