A 14-bit 2.5GS/s and 5GS/s RF sampling ADC with background calibration and dither

We describe a 14-bit 2.5GS/s non-interleaved pipelined ADC that relies on correlation-based background calibrations to correct the inter-stage gain, settling (dynamic), kick-back and memory errors. A new technique is employed to inject a large dither signal on the input to dither the non-linear kick-back on the ADC driver, and another large dither signal is injected to dither any residual non-linearity in the pipeline. In order to correct the effect of aging on the comparators, a new background calibration technique is employed to correct the comparator offsets. The ADC is fabricated as a dual in a 28nm CMOS process. An optional interleaved mode is provided, where the two ADCs on chip are time-interleaved to obtain a single 14-bit 5GS/s ADC. Background calibration of offset and gain mismatch and fixed calibration of timing mismatch between the two channels are implemented on chip.

[1]  Chun-Ying Chen,et al.  A 12-Bit 3 GS/s Pipeline ADC With 0.4 mm$^{2}$ and 500 mW in 40 nm Digital CMOS , 2012, IEEE Journal of Solid-State Circuits.

[2]  Ho-Young Lee,et al.  29.3 A 14b 1GS/s RF sampling pipelined ADC with background calibration , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

[3]  Michael Le,et al.  A 5.4GS/s 12b 500mW pipeline ADC in 28nm CMOS , 2013, 2013 Symposium on VLSI Circuits.

[4]  Matthew Martin,et al.  A 14b 2.5GS/s 8-way-interleaved pipelined ADC with background calibration and digital dynamic linearity correction , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[5]  Tao Wang,et al.  26.6 A 5GS/S 150mW 10b SHA-less pipelined/SAR hybrid ADC in 28nm CMOS , 2015, 2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers.

[6]  Gin-Kou Ma,et al.  SHA-Less Pipelined ADC With In Situ Background Clock-Skew Calibration , 2011, IEEE Journal of Solid-State Circuits.