A real-time image recognition system using a global directional-edge-feature extraction VLSI processor

A directional-edge-feature-based real-time image recognition system has been developed. By employing a digital-pixel-sensor-embedded feature extraction VLSI processor, the delay due to the image data transfer between the image sensor and the feature extraction circuits, the most serious bottleneck in such systems, has been reduced dramatically. Parallel feature vector-generation and template-matching processor functions implemented on an FPGA further accelerate the processing speed. As a result, the latency between the image capture and the final recognition has been reduced to only 906 µs, making this system suitable for time critical applications. In addition, the capability of the system for automatic adaptation to more significant features has also been experimentally demonstrated.

[1]  Daniele D. Caviglia,et al.  An analog VLSI implementation of a feature extractor for real time optical character recognition , 1998 .

[2]  Tadashi Shibata,et al.  An image representation algorithm compatible with neural-associative-processor-based hardware recognition systems , 2003, IEEE Trans. Neural Networks.

[3]  Tadashi Shibata,et al.  A Computational Digital Pixel Sensor Featuring Block-Readout Architecture for On-Chip Image Processing , 2009, IEEE Transactions on Circuits and Systems I: Regular Papers.

[4]  T. Kuroda,et al.  A 0.79-${\hbox {mm}}^{2}$ 29-mW Real-Time Face Detection Core , 2007, IEEE Journal of Solid-State Circuits.

[5]  D. Hubel,et al.  Receptive fields of single neurones in the cat's striate cortex , 1959, The Journal of physiology.

[6]  R. Genov,et al.  480-GMACS/mW Resonant Adiabatic Mixed-Signal Processor Array for Charge-Based Pattern Recognition , 2007, IEEE Journal of Solid-State Circuits.

[7]  Joo-Young Kim,et al.  A 125 GOPS 583 mW Network-on-Chip Based Parallel Processor With Bio-Inspired Visual Attention Engine , 2009, IEEE Journal of Solid-State Circuits.

[8]  Tadashi Shibata,et al.  A Digital-Pixel-Sensor-Based Global Feature Extraction VLSI for Real-Time Image Recognition , 2008 .

[9]  Donghyun Kim,et al.  A 125GOPS 583mW Network-on-Chip Based Parallel Processor with Bio-inspired Visual-Attention Engine , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[10]  T. Shibata,et al.  A real-time image-feature-extraction and vector-generation VLSI employing arrayed-shift-register architecture , 2005, Proceedings of the 31st European Solid-State Circuits Conference, 2005. ESSCIRC 2005..

[11]  T. Shibata,et al.  A delay-encoding-logic array processor for dynamic-programming matching of data sequences , 2005, IEEE Journal of Solid-State Circuits.