Simulation of a macro-pipelined multi-CPU event processor for use in FASTBUS

It is demonstrated how commercially available hardware description languages, which are normally used for hardware design verification at low to medium levels of modeling abstraction, can be used to optimize the design of complex real-time systems exhibiting concurrency. A high-performance, loosely coupled multiprocessor FASTBUS master intended for real-time event-processing applications is modeled. The performance of such a system depends on a large number of parameters that interact in a complex way, so that it becomes very difficult to make reliable tradeoffs in the design of the system architecture using an analytical approach. Given a high-level behavioral hardware description language and its simulator, it is shown that it is relatively easy to develop an executable model that provides a test bench for optimization of the architecture. >