Multiplier for DSP Application in CPS System

[1]  D. Radhakrishnan,et al.  High performance 5 : 2 compressor architectures , 2006 .

[2]  Erdem Ozcan,et al.  A High Performance Full-Word Barrett Multiplier Designed for FPGAs with DSP Resources , 2019, 2019 15th Conference on Ph.D Research in Microelectronics and Electronics (PRIME).

[3]  Dursun Baran,et al.  Energy efficient implementation of parallel CMOS multipliers with improved compressors , 2010, 2010 ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED).

[4]  Qing-Long Han,et al.  A Survey on Model-Based Distributed Control and Filtering for Industrial Cyber-Physical Systems , 2019, IEEE Transactions on Industrial Informatics.

[5]  Venkata Rama Prasad,et al.  International Journal of Reviews in Computing Artificial Neural Networks for Compression of Digital Images: a Review , 2022 .

[6]  S. Karthikeyan,et al.  Performance improvement of elliptic curve cryptography system using low power, high speed 16 × 16 Vedic multiplier based on reversible logic , 2020 .

[7]  Srinivas Devadas,et al.  Time-Predictable Computer Architecture for Cyber-Physical Systems: Digital Emulation of Power Electronics Systems , 2011, 2011 IEEE 32nd Real-Time Systems Symposium.

[8]  Peter J. Varman,et al.  High performance reliable variable latency carry select addition , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[9]  Enrico Macii,et al.  Design Techniques for NBTI-Tolerant Power-Gating Architectures , 2012, IEEE Transactions on Circuits and Systems II: Express Briefs.

[10]  Ahmad Shawahna,et al.  FPGA-Based Accelerators of Deep Learning Networks for Learning and Classification: A Review , 2019, IEEE Access.

[11]  Ajith Abraham,et al.  Artificial neural networks , 2005 .

[12]  Garrison W. Greenwood,et al.  Cyber-Physical Systems: The Next Generation of Evolvable Hardware Research and Applications , 2015 .

[13]  Jian Wang,et al.  A survey of FPGA design for AI era , 2020, Journal of Semiconductors.

[14]  Priyanka A. Patil,et al.  A Survey on Multiply Accumulate Unit , 2018, 2018 Fourth International Conference on Computing Communication Control and Automation (ICCUBEA).

[15]  Shih-Chieh Chang,et al.  Performance Optimization Using Variable-Latency Design Style , 2011, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[16]  Sanjay Pant,et al.  A self-tuning DVS processor using delay-error detection and correction , 2005, IEEE Journal of Solid-State Circuits.

[17]  Aditya Mandloi,et al.  High-speed, area efficient VLSI architecture of wallace-tree multiplier for DSP-applications , 2017, 2017 International Conference on Information, Communication, Instrumentation and Control (ICICIC).

[18]  David Bañeres,et al.  Variable-latency design by function speculation , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[19]  Michitaka Kameyama,et al.  A 32 × 32 BIT multiplier using multiple-valued MOS current-mode circuits , 1987, 1987 Symposium on VLSI Circuits.

[20]  Shubhajit Roy Chowdhury,et al.  A High Speed and Low Power 8 Bit × 8 Bit Multiplier Design Using Novel Two Transistor (2T) XOR Gates , 2015, J. Low Power Electron..

[21]  Shyh-Jye Jou,et al.  Fixed-width multiplier for DSP application , 2000, Proceedings 2000 International Conference on Computer Design.

[22]  Martin Langhammer,et al.  High Density and Performance Multiplication for FPGA , 2018, 2018 IEEE 25th Symposium on Computer Arithmetic (ARITH).