A Low-Cost BIST Based on Histogram Testing for Analog to Digital Converters

SUMMARY In this letter a histogram-based BIST (Built-In Self-Test) approach for deriving the main characteristic parameters of an ADC (Analog to Digital Converter) such as offset, gain and non-linearities is proposed. The BIST uses a ramp signal as an input signal and two counters as a response analyzer to calculate the derived static parameters. Experimental results show that the proposed method reduces the hardware overhead and testing time while detecting any static faults in an ADC.

[1]  Sungho Kang,et al.  Efficient BIST scheme for A/D converters , 2005 .

[2]  Yongsheng Wang,et al.  Optimal Schemes for ADC BIST Based on Histogram , 2005, Asian Test Symposium.

[3]  Florence Azaïs,et al.  Hardware resource minimization for histogram-based ADC BIST , 2000, Proceedings 18th IEEE VLSI Test Symposium.

[4]  Ye Yi-zheng,et al.  Optimal Schemes for ADC BIST Based on Histogram , 2005, 14th Asian Test Symposium (ATS'05).