Combined word-length optimization and high-level synthesis ofdigital signal processing systems

Conventional approaches for fixed-point implementation of digital signal processing algorithms require the scaling and word-length (WL) optimization at the algorithm level and the high-level synthesis for functional unit sharing at the architecture level. However, the algorithm-level WL optimization has a few limitations because it can neither utilize the functional unit sharing information for signal grouping nor estimate the hardware cost for each operation accurately. In this study, we develop a combined WL optimization and high-level synthesis algorithm not only to minimize the hardware implementation cost, but also to reduce the optimization time significantly. This software initially finds the WL sensitivity or minimum WL of each signal throughout fixed-point simulations of a signal flow graph, performs the WL conscious high-level synthesis where signals having the similar WL sensitivity are assigned to the same functional unit, and then conducts the final WL optimization by iteratively modifying the WLs of the synthesized hardware model. A list-scheduling-based and an integer linear-programming-based algorithms are developed for the WL conscious high-level synthesis. The hardware cost function to minimize is generated by using a synthesized hardware model. Since fixed-point simulation is used to measure the performance, this method can be applied to general, including nonlinear and time-varying, digital signal processing systems. A fourth-order infinite-impulse response filter, a fifth-order elliptic filter, and a 12th-order adaptive least mean square filter are implemented using this software.

[1]  Leland B. Jackson,et al.  On the interaction of roundoff noise and dynamic range in digital filters , 1970, Bell Syst. Tech. J..

[2]  Clifford T. Mullis,et al.  Synthesis of minimum roundoff noise fixed point digital filters , 1976 .

[3]  Giovanni De Micheli,et al.  Synthesis and Optimization of Digital Circuits , 1994 .

[4]  Seehyun Kim,et al.  Fixed-point optimization utility for C and C++ based digital signal processing programs , 1998 .

[5]  Daniel D. Gajski,et al.  High ― Level Synthesis: Introduction to Chip and System Design , 1992 .

[6]  Yu-Chin Hsu,et al.  A formal approach to the scheduling problem in high level synthesis , 1991, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[7]  Joos Vandewalle,et al.  Simulated‐annealing‐based optimization of coefficient and data word‐lengths in digital filters , 1988 .

[8]  Heinrich Meyr,et al.  System level fixed-point design based on an interpolative approach , 1997, DAC.

[9]  A. W. M. van den Enden,et al.  Discrete Time Signal Processing , 1989 .

[10]  Sun-Young Hwang,et al.  Efficient hardware optimisation algorithm for fixed point digital signal processing ASIC design , 1996 .

[11]  A. Constantinides,et al.  Finite word length FIR filter design using integer programming over a discrete coefficient space , 1982 .

[12]  H. De Man,et al.  Automatic synthesis of signal processing benchmark using the CATHEDRAL silicon compilers , 1988, Proceedings of the IEEE 1988 Custom Integrated Circuits Conference.

[13]  R. Hartley,et al.  Digit-Serial Computation , 1995 .

[14]  C. Inacio,et al.  The DSP decision: fixed point or floating? , 1996 .

[15]  Wonyong Sung,et al.  Simulation-based word-length optimization method for fixed-point digital signal processing systems , 1995, IEEE Trans. Signal Process..

[16]  Seehyun Kim,et al.  A floating-point to fixed-point assembly program translator for the TMS 320C25 , 1994 .