Reining in the Functional Verification of Complex Processor Designs with Automation, Prioritization, and Approximation

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[1]  Alain Greiner,et al.  An Efficient TLM/T Modeling and Simulation Environment Based on Conservative Parallel Discrete Event Principles , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[2]  Kwang-Ting Cheng,et al.  A case study of Time-Multiplexed Assertion Checking for post-silicon debugging , 2010, 2010 IEEE International High Level Design Validation and Test Workshop (HLDVT).

[3]  Monica Farkash,et al.  Data mining diagnostics and bug MRIs for HW bug localization , 2015, 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[4]  Francesco Zappa Nardelli,et al.  x86-TSO , 2010, Commun. ACM.

[5]  G.E. Moore,et al.  Cramming More Components Onto Integrated Circuits , 1998, Proceedings of the IEEE.

[6]  Sarita V. Adve,et al.  Trace-based microarchitecture-level diagnosis of permanent hardware faults , 2008, 2008 IEEE International Conference on Dependable Systems and Networks With FTCS and DCC (DSN).

[7]  P. Cochat,et al.  Et al , 2008, Archives de pediatrie : organe officiel de la Societe francaise de pediatrie.

[8]  Trevor Mudge,et al.  Razor: a low-power pipeline based on circuit-level timing speculation , 2003, Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36..

[9]  Vitali Sokhin,et al.  Threadmill: A post-silicon exerciser for multi-threaded processors , 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).

[10]  Nikil D. Dutt,et al.  Graph-based functional test program generation for pipelined processors , 2004, Proceedings Design, Automation and Test in Europe Conference and Exhibition.

[11]  Jongshin Shin,et al.  A genetic approach to automatic bias generation for biased random instruction generation , 2001, Proceedings of the 2001 Congress on Evolutionary Computation (IEEE Cat. No.01TH8546).

[12]  M. R. Woodward,et al.  Mutation testing - its origin and evolution , 1993, Inf. Softw. Technol..

[13]  Azadeh Davoodi,et al.  Multi-mode trace signal selection for post-silicon debug , 2014, 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC).

[14]  Andreas G. Veneris,et al.  Exemplar-based failure triage for regression design debugging , 2015, 2015 16th Latin-American Test Symposium (LATS).

[15]  Qi Guo,et al.  Coverage Directed Test Generation: Godson Experience , 2008, 2008 17th Asian Test Symposium.

[16]  Valeria Bertacco,et al.  Machine learning-based anomaly detection for post-silicon bug diagnosis , 2013, 2013 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[17]  Klaus-Dieter Schubert,et al.  Post-silicon validation of the IBM POWER8 processor , 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).

[18]  Qiang Xu,et al.  Trace signal selection for visibility enhancement in post-silicon validation , 2009, 2009 Design, Automation & Test in Europe Conference & Exhibition.

[19]  Nikil D. Dutt,et al.  Functional coverage driven test generation for validation of pipelined processors , 2005, Design, Automation and Test in Europe.

[20]  Francesco Zappa Nardelli,et al.  The semantics of power and ARM multiprocessor machine code , 2009, DAMP '09.

[21]  Avi Ziv,et al.  Coverage directed test generation for functional verification using Bayesian networks , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[22]  Brian Bailey,et al.  ESL Models and their Application: Electronic System Level Design and Verification in Practice , 2009 .

[23]  Nello Cristianini,et al.  An Introduction to Support Vector Machines and Other Kernel-based Learning Methods , 2000 .

[24]  Amitabha Roy,et al.  Fast and Generalized Polynomial Time Memory Consistency Verification , 2006, CAV.

[25]  Mátyás A. Sustik,et al.  Robust partitioning for hardware-accelerated functional verification , 2011, 2011 48th ACM/EDAC/IEEE Design Automation Conference (DAC).

[26]  Milo M. K. Martin,et al.  Multifacet's general execution-driven multiprocessor simulator (GEMS) toolset , 2005, CARN.

[27]  Zeljko Zilic,et al.  Adding Debug Enhancements to Assertion Checkers for Hardware Emulation and Silicon Debug , 2006, 2006 International Conference on Computer Design.

[28]  R. K. Shyamasundar,et al.  Introduction to algorithms , 1996 .

[29]  Allon Adir,et al.  Genesys-Pro: innovations in test program generation for functional processor verification , 2004, IEEE Design & Test of Computers.

[30]  Anant Agarwal,et al.  Logic emulation with virtual wires , 1997, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[31]  Dennis Shasha,et al.  Efficient and correct execution of parallel programs that share memory , 1988, TOPL.

[32]  Pallab Dasgupta,et al.  Synthesis of System Verilog Assertions , 2006, Proceedings of the Design Automation & Test in Europe Conference.

[33]  Igor L. Markov,et al.  Logic synthesis and circuit customization using extensive external don't-cares , 2010, TODE.

[34]  Wolfgang Roesner,et al.  Comprehensive Functional Verification: The Complete Industry Cycle (Systems on Silicon) , 2005 .

[35]  Farzan Fallah,et al.  Quick detection of difficult bugs for effective post-silicon validation , 2012, DAC Design Automation Conference 2012.

[36]  Toshihiro Hattori,et al.  4.4 A 197mW 70ms-latency full-HD 12-channel video-processing SoC for car information systems , 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

[37]  Satish Narayanasamy,et al.  DRFX: a simple and efficient memory model for concurrent programming languages , 2010, PLDI '10.

[38]  Prabhat Mishra,et al.  Efficient Trace Signal Selection for Post Silicon Validation and Debug , 2011, 2011 24th Internatioal Conference on VLSI Design.

[39]  Jade Alglave,et al.  Understanding POWER multiprocessors , 2011, PLDI '11.

[40]  Azadeh Davoodi,et al.  Trace signal selection to enhance timing and logic visibility in post-silicon validation , 2010, 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[41]  Valeria Bertacco,et al.  Post-silicon verification for cache coherence , 2008, 2008 IEEE International Conference on Computer Design.

[42]  Kurt Keutzer,et al.  Coverage Metrics for Functional Validation of Hardware Designs , 2001, IEEE Des. Test Comput..

[43]  Albert Meixner,et al.  Dynamic Verification of Memory Consistency in Cache-Coherent Multithreaded Computer Architectures , 2006, International Conference on Dependable Systems and Networks (DSN'06).

[44]  Sean Safarpour,et al.  From RTL to silicon: The case for automated debug , 2011, 16th Asia and South Pacific Design Automation Conference (ASP-DAC 2011).

[45]  Sanjay J. Patel,et al.  ReStore: Symptom-Based Soft Error Detection in Microprocessors , 2006, IEEE Trans. Dependable Secur. Comput..

[46]  Ioannis Papaefstathiou,et al.  Efficient Testbench Code Synthesis for a Hardware Emulator System , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

[47]  Jie Han,et al.  Approximate computing: An emerging paradigm for energy-efficient design , 2013, 2013 18th IEEE European Test Symposium (ETS).

[48]  Ilan Beer,et al.  FoCs: Automatic Generation of Simulation Checkers from Formal Specifications , 2000, CAV.

[49]  Greg Hamerly,et al.  SimPoint 3.0: Faster and More Flexible Program Analysis , 2005 .

[50]  Eric Rotenberg,et al.  FabScalar: Composing synthesizable RTL designs of arbitrary cores within a canonical superscalar template , 2011, 2011 38th Annual International Symposium on Computer Architecture (ISCA).

[51]  Kerstin Eder,et al.  Introducing XCS to Coverage Directed test Generation , 2011, 2011 IEEE International High Level Design Validation and Test Workshop.

[52]  Sridhar Narayanan,et al.  TSOtool: a program for verifying memory systems using the memory consistency model , 2004, Proceedings. 31st Annual International Symposium on Computer Architecture, 2004..

[53]  Jade Alglave,et al.  Litmus: Running Tests against Hardware , 2011, TACAS.

[54]  Ethem Alpaydin,et al.  Introduction to machine learning , 2004, Adaptive computation and machine learning.

[55]  Bob Bentley,et al.  Validating the Intel(R) Pentium(R) 4 microprocessor , 2001, Proceedings of the 38th Design Automation Conference (IEEE Cat. No.01CH37232).

[56]  Kenneth L. McMillan,et al.  Approximation and decomposition of binary decision diagrams , 1998, Proceedings 1998 Design and Automation Conference. 35th DAC. (Cat. No.98CH36175).

[57]  Sparsh Mittal,et al.  A Survey of Techniques for Approximate Computing , 2016, ACM Comput. Surv..

[58]  Zeljko Zilic,et al.  Efficient Automata-Based Assertion-Checker Synthesis of PSL Properties , 2006, 2006 IEEE International High Level Design Validation and Test Workshop.

[59]  Smruti R. Sarangi,et al.  A survey of checker architectures , 2013, CSUR.

[60]  Avi Ziv,et al.  Checking architectural outputs instruction-by-instruction on acceleration platforms , 2012, DAC Design Automation Conference 2012.

[61]  Jason Cong,et al.  Accelerator-rich architectures: Opportunities and progresses , 2014, 2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC).

[62]  Harry D. Foster.  Trends in functional verification: A 2014 industry study , 2015, 2015 52nd ACM/EDAC/IEEE Design Automation Conference (DAC).

[63]  Mikko H. Lipasti,et al.  Constraint graph analysis of multithreaded programs , 2003, 2003 12th International Conference on Parallel Architectures and Compilation Techniques.

[64]  Sharad Malik,et al.  Runtime validation of memory ordering using constraint graph checking , 2008, 2008 IEEE 14th International Symposium on High Performance Computer Architecture.

[65]  Leslie Lamport,et al.  How to Make a Multiprocessor Computer That Correctly Executes Multiprocess Programs , 2016, IEEE Transactions on Computers.

[66]  Gérard Memmi,et al.  A reconfigurable design-for-debug infrastructure for SoCs , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[67]  Sanjay Gupta,et al.  Verification of the Cell Broadband Engine/spl trade/ processor , 2006, DAC 2006.

[68]  Masahiro Fujita,et al.  Verification Techniques for System-Level Design , 2007, The Morgan Kaufmann series in systems on silicon.

[69]  Kerstin Eder,et al.  Coverage-Directed Test Generation Automated by Machine Learning -- A Review , 2012, ACM Trans. Design Autom. Electr. Syst..

[70]  Allon Adir,et al.  Dynamic Selection of Trace Signals for Post-Silicon Debug , 2013, 2013 14th International Workshop on Microprocessor Test and Verification.

[71]  Sarita V. Adve,et al.  Shared Memory Consistency Models: A Tutorial , 1996, Computer.

[72]  David Blaauw,et al.  Opportunities and challenges for better than worst-case design , 2005, ASP-DAC.

[73]  Wolfgang Rosenstiel,et al.  Coverage Driven Verification applied to Embedded Software , 2007, IEEE Computer Society Annual Symposium on VLSI (ISVLSI '07).

[74]  Kamran Rahmani,et al.  Efficient Selection of Trace and Scan Signals for Post-Silicon Debug , 2016, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[75]  Rajeev Alur,et al.  Generating Litmus Tests for Contrasting Memory Consistency Models , 2010, CAV.

[76]  Valeria Bertacco,et al.  Dacota: Post-silicon validation of the memory subsystem in multi-core designs , 2009, 2009 IEEE 15th International Symposium on High Performance Computer Architecture.

[77]  Lizy Kurian John,et al.  Automatic Generation of Miniaturized Synthetic Proxies for Target Applications to Efficiently Design Multicore Processors , 2014, IEEE Transactions on Computers.

[78]  Eman El Mandouh,et al.  Covgen: A framework for automatic extraction of functional coverage models , 2016, 2016 17th International Symposium on Quality Electronic Design (ISQED).

[79]  David Lin,et al.  A structured approach to post-silicon validation and debug using symbolic quick error detection , 2015, 2015 IEEE International Test Conference (ITC).

[80]  Valeria Bertacco,et al.  Simulation-based signal selection for state restoration in silicon debug , 2011, 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[81]  Vitali Sokhin,et al.  Effective post-silicon failure localization using dynamic program slicing , 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[82]  Arvind,et al.  Memory Model = Instruction Reordering + Store Atomicity , 2006, 33rd International Symposium on Computer Architecture (ISCA'06).

[83]  Scott Mahlke,et al.  Low cost control flow protection using abstract control signatures , 2013, LCTES '13.

[84]  David A. Wood,et al.  A Primer on Memory Consistency and Cache Coherence , 2012, Synthesis Lectures on Computer Architecture.

[85]  Enamul Amyeen,et al.  Microprocessor system failures debug and fault isolation methodology , 2009, 2009 International Test Conference.