Analyzing testability from behavioral to RT level

In this paper, we present a method for analyzing the testability of a circuit during high level synthesis. The testability analysis returns values that represent the relative difficulty for computing test data, whatever the level of description of a circuit is (from the behavioral level-initial specification-down to the Register Transfer Level-high level synthesis output-). Experiments show the good correlation of the so-obtained testability measures with gate-level testability measures (e.g. Scoap). The proposed measures are used to guide high level synthesis towards the generation of easily SATPG testable datapaths.

[1]  Niraj K. Jha,et al.  Behavioral Synthesis of Highly Testable Data Paths under the Non-Scan and Partial Scan Environments , 1993, 30th ACM/IEEE Design Automation Conference.

[2]  Pierre G. Paulin,et al.  Scheduling and Binding Algorithms for High-Level Synthesis , 1989, 26th ACM/IEEE Design Automation Conference.

[3]  Bruno Rouzeyre,et al.  High-level synthesis for easy testability , 1995, Proceedings the European Design and Test Conference. ED&TC 1995.

[4]  Hans-Joachim Wunderlich,et al.  Synthesis of self-testable controllers , 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.

[5]  Niraj K. Jha,et al.  Genesis: a behavioral synthesis system for hierarchical testability , 1994, Proceedings of European Design and Test Conference EDAC-ETC-EUROASIC.

[6]  S. Freeman.  Test generation for data-path logic: the F-path method , 1988 .

[7]  Rajiv Jain,et al.  Experience with the ADAM Synthesis System , 1989, 26th ACM/IEEE Design Automation Conference.

[8]  Daniel G. Saab,et al.  Accessibility analysis on data flow graph: an approach to design for testability , 1991, [1991 Proceedings] IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[9]  Daniel P. Siewiorek,et al.  Automated Synthesis of Data Paths in Digital Systems , 1986, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[10]  A. Mujumdar,et al.  Incorporating testability considerations in high-level synthesis , 1992, [1992] Digest of Papers. FTCS-22: The Twenty-Second International Symposium on Fault-Tolerant Computing.