Impact of High-$\kappa$ Offset Spacer in 65-nm Node SOI Devices

In this letter, 65-nm node silicon-on-insulator devices with high-kappa offset spacer dielectric were investigated by extensive 2-D device simulation. The result shows that the high-kappa offset spacer dielectric can effectively increase the on-state driving current ION and reduce the off leakage current IOFF due to the high vertical fringing electric field effect. This fringing field can significantly improve the ION/IOFF current ratio and the subthreshold swing compared with the conventional oxide spacer. Consequently, the gate-to-channel control ability is enhanced by the fringing field via the high-kappa offset spacer dielectric

[1]  V. Trivedi,et al.  Nanoscale FinFETs with gate-source/drain underlap , 2005, IEEE Transactions on Electron Devices.

[2]  R. Han,et al.  Source/Drain Resistance of UTB SOI MOSFET , 2005, 2005 IEEE Conference on Electron Devices and Solid-State Circuits.

[3]  V. Narayanan,et al.  Device design considerations for ultra-thin SOI MOSFETs , 2003, IEEE International Electron Devices Meeting 2003.

[4]  Chenming Hu,et al.  45nm node planar-SOI technology with 0.296 /spl mu/m/sup 2/ 6T-SRAM cell , 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

[5]  Chenming Hu,et al.  45nm node planar-SOI technology with 0.296μm2 6T-SRAM cell , 2004, VLSIT 2004.

[6]  Bing-Yue Tsui,et al.  A comprehensive study on the FIBL of nanoscale MOSFETs , 2004 .

[7]  Haitao Liu,et al.  A novel self-aligned offset-gated polysilicon TFT using high-/spl kappa/ dielectric spacers , 2004, IEEE Electron Device Letters.

[8]  A new LDD structure: total overlap with polysilicon spacer (TOPS) , 1990, IEEE Electron Device Letters.

[9]  Tsai-Sheng Gau,et al.  Novel 20nm hybrid SOI/bulk CMOS technology with 0.183/spl mu/m/sup 2/ 6T-SRAM cell by immersion lithography , 2005, Digest of Technical Papers. 2005 Symposium on VLSI Technology, 2005..

[10]  S. Mason.  Power Gain in Feedback Amplifier , 1954 .

[11]  J. Yugami,et al.  Femto-second CMOS technology with high-k offset spacer and SiN gate dielectric with oxygen-enriched interface , 2002, 2002 Symposium on VLSI Technology. Digest of Technical Papers (Cat. No.01CH37303).

[12]  J. Conner,et al.  Fully-depleted SOI devices with TaSiN gate, HfO2 gate dielectric, and elevated source/drain extensions , 2003, IEEE Electron Device Letters.

[13]  F. Danneville,et al.  What are the limiting parameters of deep-submicron MOSFETs for high frequency applications? , 2003, IEEE Electron Device Letters.

[14]  Masataka Kase,et al.  High performance 35 nm gate CMOSFETs with vertical scaling and total stress control for 65 nm technology , 2003, 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407).

[15]  S. Mudanai,et al.  Source-side barrier effects with very high-K dielectrics in 50 nm Si MOSFETs , 1999, 1999 57th Annual Device Research Conference Digest (Cat. No.99TH8393).

[16]  High performance 30 nm bulk CMOS for 65 nm technology node (CMOS5) , 2002, Digest. International Electron Devices Meeting,.

[17]  Chenming Hu,et al.  A 65nm node strained SOI technology with slim spacer , 2003, IEEE International Electron Devices Meeting 2003.

[18]  Haitao Liu,et al.  Characteristics of high-K spacer offset-gated polysilicon TFTs , 2004, IEEE Transactions on Electron Devices.