Resource allocation for coarse-grain FPGA development

The development of domain-specialized reconfigurable devices, and even the nature of domains themselves, has been largely unexplored. In part this is because the same architectural improvements that allow domain-specialized field programmable gate arrays (FPGAs) to outperform conventional reconfigurable devices also significantly change the design problem. The migration from completely generic lookup tables (LUTs) and highly connected routing fabrics to specialized coarse-grain functional units and very structured communication resources presents designers with the problem of how to best customize the system based upon anticipated usage. In this paper, the authors establish the nature of many of these problems and illustrate the difficulties of determining the appropriate number and ratio of functional units considering the demands of a diverse domain. The authors present three algorithms that attempt to balance the hardware needs of the domain while considering design constraints such as the performance and area of the system.

[1]  Josef Pieprzyk,et al.  Introducing the new LOKI97 Block Cipher , 1998 .

[2]  Barruquer Moner.  IX. References , 1971 .

[3]  Scott Hauck,et al.  Track Placement: Orchestrating Routing Structures to Maximize Routability , 2003, FPL.

[4]  Carl Ebeling,et al.  Architecture design of reconfigurable pipelined datapaths , 1999, Proceedings 20th Anniversary Conference on Advanced Research in VLSI.

[5]  Jonathan Rose,et al.  The effect of LUT and cluster size on deep-submicron FPGA performance and density , 2004 .

[6]  James Foti,et al.  Status of the Advanced Encryption Standard (AES) Development Effort , 1999 .

[7]  Monica S. Lam,et al.  Multiprocessors from a software perspective , 1996, IEEE Micro.

[8]  Carl Ebeling,et al.  RaPiD - Reconfigurable Pipelined Datapath , 1996, FPL.

[9]  Scott Hauck,et al.  Flexible Routing Architecture Generation for Domain-Specific Reconfigurable Subsystems , 2002, FPL.

[10]  Joan Daemen,et al.  AES Proposal : Rijndael , 1998 .

[11]  Scott Hauck,et al.  Totem: Custom Reconfigurable Array Generation , 2001, The 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM'01).

[12]  Shai Halevi,et al.  MARS - a candidate cipher for AES , 1999 .

[13]  Ross Anderson,et al.  Serpent: A Proposal for the Advanced Encryption Standard , 1998 .

[14]  Vaughn Betz,et al.  FPGA routing architecture: segmentation and buffering to optimize speed and density , 1999, FPGA '99.

[15]  Vaughn Betz,et al.  VPR: A new packing, placement and routing tool for FPGA research , 1997, FPL.

[16]  Jeff Gilchrist,et al.  The CAST-256 Encryption Algorithm , 1999, RFC.

[17]  RoseJonathan,et al.  The effect of LUT and cluster size on deep-submicron FPGA performance and density , 2004 .

[18]  Kenneth Eguro.  RaPiD-AES: Developing an Encryption-Specific FPGA Architecture , 2002 .