Executable Micro-Architecture Modeling and Automatic Verification of EtherCAT

EtherCAT as a real-time Ethernet field-bus protocol has been extensively used in a variety of service-oriented robots. The functional correctness in EtherCAT is crucial to ensure the safe and reliable operation of service robots. It is hard to completely verify the correctness of a concurrent system by traditional simulation or emulation, and formal verification is a good complement to that, but state-based model checking of formal method could result in the state space explosion problem when high-level properties are verified. In order to verify its high-level properties automatically while preserving the underlying circuit structure of EtherCAT, eXecutable Micro-Architecture Specification (xMAS) is used to describe EtherCAT communication system for robots and data-flow oriented model is set up in the form of xMAS network. This formal model provides accurate and intuitive graphical representation for architecture of EtherCAT communication system, which describes its sufficiently detailed timing and functionality. The properties of functional correctness in EtherCAT communication system are automatically verified in ACL2 (A Computational Logic for Application Common Lisp), and the verification results are shown to be satisfied. This work provides a useful reference for the circuit design of the EtherCAT communication system in robots under the guidance of verification.

[1]  Ümit Y. Ogras,et al.  Quick formal modeling of communication fabrics to enable verification , 2010, 2010 IEEE International High Level Design Validation and Test Workshop (HLDVT).

[2]  P. Cochat,et al.  Et al , 2008, Archives de pediatrie : organe officiel de la Societe francaise de pediatrie.

[3]  Michael Kishinevsky,et al.  Automatic generation of inductive invariants from high-level microarchitectural models of communication fabrics , 2012, Formal Methods Syst. Des..

[4]  Julien Schmaltz,et al.  Hunting deadlocks efficiently in microarchitectural models of communication fabrics , 2011, 2011 Formal Methods in Computer-Aided Design (FMCAD).

[5]  J. Strother Moore,et al.  Symbolic Simulation: An ACL2 Approach , 1998, FMCAD.

[6]  Julien Schmaltz,et al.  Easy Formal Specification and Validation of Unbounded Networks-on-Chips Architectures , 2012, TODE.

[7]  Julien Schmaltz,et al.  A formalisation of XMAS , 2013, ACL2.

[8]  Laurence Pierre,et al.  A Generic Model for Formally Verifying NoC Communication Architectures: A Case Study , 2007, First International Symposium on Networks-on-Chip (NOCS'07).

[9]  Julien Schmaltz,et al.  Inference of channel types in micro-architectural models of on-chip communication networks , 2014, 2014 22nd International Conference on Very Large Scale Integration (VLSI-SoC).

[10]  Panagiotis Manolios,et al.  Computer-aided reasoning : ACL2 case studies , 2000 .

[11]  Michael Kishinevsky,et al.  Verifying Deadlock-Freedom of Communication Fabrics , 2011, VMCAI.

[12]  Jie Zhang,et al.  基于xMAS模型的SpaceWire信誉逻辑的形式化验证 (xMAS-based Formal Verification of SpaceWire Credit Logic) , 2016, 计算机科学.

[13]  Yang Jie.  Research of robot control bus scheme based on EtherCAT , 2013 .

[14]  Huan Ji.  EtherCAT-Industrial Ethernet Fieldbus and Its Driver Design , 2007 .

[15]  Santosh Biswas,et al.  xMAS Based Accurate Modeling and Progress Verification of NoCs , 2017, VDAT.

[16]  Ulrich Schmucker,et al.  WALKING ROBOT “ANTON”: DESIGN, SIMULATION, EXPERIMENTS , 2008 .

[17]  Julien Schmaltz,et al.  A Generic Network on Chip Model , 2005, TPHOLs.