A submicron triple-level-metal gate array process utilizing tungsten for 1st level interconnect

A novel triple-level-metal process, utilizing tungsten for first-level metallization, has been developed for use in submicron arrays. The contact barrier is a composite layer of sputtered and CVD TiN, providing for good adhesion of the blanket tungsten layer. Other process modules include tapered contact and via etches, dyed resist for fine-line patterning, reflowed BPSG for first ILD and via-1, and low-stress nitride passivation, providing for void-free metallization for all three layers. Prototype 1.0- mu m gate arrays have been fabricated using this technology.<<ETX>>