The BubbleWrap many-core: Popping cores for sequential acceleration

Many-core scaling now faces a power wall. The gap between the number of cores that fit on a die and the number that can operate simultaneously under the power budget is rapidly increasing with technology scaling. In future designs, many of the cores may have to be dormant at any given time to meet the power budget. To push back the many-core power wall, this paper proposes Dynamic Voltage Scaling for Aging Management (DVSAM) - a new scheme for managing processor aging to attain higher performance or lower power consumption. In addition, this paper introduces the BubbleWrap many-core, a novel architecture that makes extensive use of DVSAM. BubbleWrap identifies the most power-efficient set of cores in a variation-affected chip-the largest set that can be simultaneously powered-on - and designates them as Throughput cores dedicated to parallel-section execution. The rest of the cores are designated as Expendable and are dedicated to accelerating sequential sections. BubbleWrap attains maximum sequential acceleration by sacrificing Expendable cores one at a time, running them at elevated supply voltage for a significantly shorter service life each, until they completely wear-out and are discarded - figuratively, as if popping bubbles in bubble wrap that protects Throughput cores. In simulated 32-core chips, BubbleWrap provides substantial improvements over a plain chip. For example, on average, one design runs fully-sequential applications at a 16% higher frequency, and fully-parallel ones with a 30% higher throughput.

[1]  D.A. Antoniadis,et al.  MOSFET Performance Scaling—Part II: Future Directions , 2008, IEEE Transactions on Electron Devices.

[2]  Josep Torrellas,et al.  Facelift: Hiding and slowing down aging in multicores , 2008, 2008 41st IEEE/ACM International Symposium on Microarchitecture.

[3]  David Blaauw,et al.  Energy efficient near-threshold chip multi-processing , 2007, Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07).

[4]  C.H. Kim,et al.  Silicon Odometer: An On-Chip Reliability Monitor for Measuring Frequency Degradation of Digital Circuits , 2007, 2007 IEEE Symposium on VLSI Circuits.

[5]  Pradip Bose,et al.  The case for lifetime reliability-aware microprocessors , 2004, Proceedings. 31st Annual International Symposium on Computer Architecture, 2004..

[6]  J. Hicks.  45nm Transistor Reliability , 2008 .

[7]  Pradip Bose,et al.  Exploiting structural duplication for lifetime reliability enhancement , 2005, 32nd International Symposium on Computer Architecture (ISCA'05).

[8]  Ishiuchi,et al.  Alpha-Power Law MOSFET Model and its Applications to CMOS Inverter Delay and Other Formulas , 2004 .

[9]  Josep Torrellas,et al.  Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing , 2007, 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007).

[10]  Pradip Bose,et al.  A Proactive Wearout Recovery Approach for Exploiting Microarchitectural Redundancy to Extend Cache SRAM Lifetime , 2008, 2008 International Symposium on Computer Architecture.

[11]  John Keane,et al.  An All-In-One Silicon Odometer for Separately Monitoring HCI, BTI, and TDDB , 2010, IEEE Journal of Solid-State Circuits.

[12]  J. W. McPherson,et al.  Reliability challenges for 45nm and beyond , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[13]  R.H. Dennard,et al.  Design Of Ion-implanted MOSFET's with Very Small Physical Dimensions , 1974, Proceedings of the IEEE.

[14]  Robert H. Dennard,et al.  Design of ion-implanted MOSFET's with very small physical dimensions , 2007 .

[15]  K. Bernstein,et al.  Scaling, power, and the future of CMOS , 2005, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest..

[16]  Ming Zhang,et al.  Circuit Failure Prediction and Its Application to Transistor Aging , 2007, 25th IEEE VLSI Test Symposium (VTS'07).

[17]  Babak Falsafi,et al.  Detecting Emerging Wearout Faults , 2007 .

[18]  K. Jenkins,et al.  On-Chip circuit for monitoring frequency degradation due to NBTI , 2008, 2008 IEEE International Reliability Physics Symposium.

[19]  B. M. Gordon,et al.  Supply and threshold voltage scaling for low power CMOS , 1997, IEEE J. Solid State Circuits.

[20]  Eby G. Friedman,et al.  Power Distribution Networks with On-Chip Decoupling Capacitors , 2007 .

[21]  Yu Cao,et al.  New generation of predictive technology model for sub-45nm design exploration , 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).

[22]  Kevin Skadron,et al.  Many-core design from a thermal perspective , 2008, 2008 45th ACM/IEEE Design Automation Conference.

[23]  Scott A. Mahlke,et al.  Bridging the computation gap between programmable processors and hardwired accelerators , 2009, 2009 IEEE 15th International Symposium on High Performance Computer Architecture.

[24]  Josep Torrellas,et al.  Variation-Aware Application Scheduling and Power Management for Chip Multiprocessors , 2008, 2008 International Symposium on Computer Architecture.

[25]  Yu Cao,et al.  Compact Modeling and Simulation of Circuit Reliability for 65-nm CMOS Technology , 2007, IEEE Transactions on Device and Materials Reliability.

[26]  Chris Auth,et al.  45nm high-k + metal gate strain-enhanced CMOS transistors , 2008, 2008 IEEE Custom Integrated Circuits Conference.

[27]  S. Samavedam,et al.  32nm general purpose bulk CMOS technology for high performance applications at low voltage , 2008, 2008 IEEE International Electron Devices Meeting.

[28]  R. Kumar,et al.  An Integrated Quad-Core Opteron Processor , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[29]  G. Dewey,et al.  BTI reliability of 45 nm high-K + metal-gate process technology , 2008, 2008 IEEE International Reliability Physics Symposium.

[30]  Shuguang Feng,et al.  Self-calibrating Online Wearout Detection , 2007, 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007).

[31]  Edward J. Nowak,et al.  Maintaining the benefits of CMOS scaling when scaling bogs down , 2002, IBM J. Res. Dev..

[32]  Sani R. Nassif,et al.  High Performance CMOS Variability in the 65nm Regime and Beyond , 2006, 2007 IEEE International Electron Devices Meeting.

[33]  Jaume Abella,et al.  Penelope: The NBTI-Aware Processor , 2007, 40th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO 2007).

[34]  David Blaauw,et al.  Compact In-Situ Sensors for Monitoring Negative-Bias-Temperature-Instability Effect and Oxide Degradation , 2008, 2008 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[35]  Margaret Martonosi,et al.  Wattch: a framework for architectural-level power analysis and optimizations , 2000, Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201).