论文信息 - Fully depleted SOI process and device technology for digital and RF applications

Fully depleted SOI process and device technology for digital and RF applications

Abstract This work demonstrates suitability of FD-SOI devices for low power digital and RF applications for wireless communication. FD-SOI CMOS offers an approximately 60% power reduction over bulk CMOS while maintaining operation speed. Passive devices for RF applications exhibit excellent Q values. In particular, cross-talk immunity at gigahertz range is superior to the bulk. These are very attractive for mixed signal circuits in the gigahertz era.

[1] Jean-Pierre Colinge,et al. Fully-depleted SOI CMOS for analog applications , 1998 .

[2] N. Hirashita,et al. Fully-depleted SOI CMOSFETs with the fully-silicided source/drain structure , 2002 .

[3] J.E. Chung,et al. Reduction of threshold voltage sensitivity in SOI MOSFET's , 1995, IEEE Electron Device Letters.

[4] G. G. Shahidi. SOI technology for the GHz era , 2002, IBM J. Res. Dev..

[5] L. T. Su,et al. Deep-submicrometer channel design in silicon-on-insulator (SOI) MOSFET's , 1994, IEEE Electron Device Letters.

[6] D. Flandre,et al. Demonstration of the potential of accumulation-mode MOS transistors on SOI substrates for high-temperature operation (150-300 degrees C) , 1993, IEEE Electron Device Letters.

[7] A. Yamagishi,et al. 2-GHz RF front-end circuits in CMOS/SIMOX operating at an extremely low voltage of 0.5 V , 2000, IEEE Journal of Solid-State Circuits.