Conditional pre-charge techniques for power-efficient dual-edge clocking

A new dual edge-triggered flip-flop that saves power by inhibiting transitions of the nodes that are not used to change the state is presented. The proposed flip-flop is 12% faster with 10% lower Energy-Delay Product for 50% data activity, as compared to the previously published dual edge-triggered storage elements. This was confirmed by simulation using 0.18um process, 1.8V power supply, and clock frequency of 250MHz. This flip-flop is particularly suitable for low-power applications.

[1]  Madhavan Swaminathan,et al.  Optimal sequencing energy allocation for CMOS integrated systems , 2002, Proceedings International Symposium on Quality Electronic Design.

[2]  A. Kumar,et al.  A 1.2 GHz Alpha microprocessor with 44.8 GB/s chip pin bandwidth , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[3]  F. Klass.  Semi-dynamic and dynamic flip-flops with embedded logic , 1998, 1998 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.98CH36215).

[4]  Vojin G. Oklobdzija,et al.  High-performance system design : circuits and logic , 1999 .

[5]  Vojin G. Oklobdzija,et al.  Timing characterization of dual-edge triggered flip-flops , 2001, Proceedings 2001 IEEE International Conference on Computer Design: VLSI in Computers and Processors. ICCD 2001.

[6]  Chuan Yi Tang,et al.  A 2.|E|-Bit Distributed Algorithm for the Directed Euler Trail Problem , 1993, Inf. Process. Lett..

[7]  N. Nedovic,et al.  Hybrid latch flip-flop with improved power efficiency , 2000, Proceedings 13th Symposium on Integrated Circuits and Systems Design (Cat. No.PR00843).

[8]  B. Flachs,et al.  A 1 GHz single-issue 64 b PowerPC processor , 2000, 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056).

[9]  James Tschanz,et al.  Comparative delay and energy of single edge-triggered & dual edge-triggered pulsed flip-flops for high-performance microprocessors , 2001, ISLPED '01.

[10]  F. Weber,et al.  Flow-through latch and edge-triggered flip-flop hybrid elements , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[11]  P. Bannon,et al.  A 433 MHz 64 b quad issue RISC microprocessor , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[12]  Manoj Sachdev,et al.  Low power, testable dual edge triggered flip-flops , 1996, Proceedings of 1996 International Symposium on Low Power Electronics and Design.

[13]  Hector Sanchez,et al.  A 2.2 W, 80 MHz superscalar RISC microprocessor , 1994 .

[14]  Vladimir Stojanovic,et al.  Comparative analysis of master-slave latches and flip-flops for high-performance and low-power systems , 1999, IEEE J. Solid State Circuits.

[15]  A. Gago,et al.  Reduced implementation of D-type DET flip-flops , 1993 .