80 nm polysilicon gated n-FETs with ultra-thin Al/sub 2/O/sub 3/ gate dielectric for ULSI applications

This work demonstrates the integration of Al/sub 2/O/sub 3/ gate-dielectrics into a sub 0.1 /spl mu/m n-MOS process using polycrystalline silicon gates, Devices incorporating Al/sub 2/O/sub 3/ films with a dielectric constant /spl epsi/-11 and electrical thickness t/sub qm/<1.5 nm have been fabricated. Gate leakage currents are /spl sim/100 times lower than those found in SiO/sub 2/ films of equivalent thickness. Encouraging device characteristics are shown. Charging due to slow states and/or fixed charge have been shown to be in the 100 mV range which may be related to the somewhat reduced mobility. The room temperature reliability of these devices based upon the values of /spl beta/ (Weibull slope) and /spl gamma/ (voltage acceleration) suggest that the Al/sub 2/O/sub 3/ lifetime may exceed that of SiO/sub 2/ films.