Filter for Noise Reduction Application

the parallel form in ldaptive IIR filteling is an elficient realization that provides robust stability monitoring with less complexity than that of the direct form. This paper presents an implementation of two line parallel structure employing a real orthogonal transform and real coefficienb second-order section as suh fiters on FPGA. Architecture that is implemented is in pipeline fashion and it is independent from its building tl~ocks and they may have its own implementation or in other system numbering. In the last section, we compared throughput of our architecture with a Ti DSP ~MS32OC3~/4x), the results show that this architecture works better than the DSP.