Defect avoidance in a 3-D heterogeneous sensor [acoustic/seismic/active pixel/IR imaging sensor array]

A 3D heterogeneous sensor using a stacked chip is investigated. Optical active pixel sensor (APS) and IR bolometer detectors are combined to create a multispectral pixel for aligned color and infrared imaging. An acoustic and seismic micromachined sensor array obtains sound spectral and directional information. For the optical/IR imagers, fault tolerant APS cells and software methods are used for defect avoidance. For the acoustic/seismic array, spare detectors are combined with signal processing to compensate for changes in detector positions due to defects. The sensor fault distribution in turn impacts the defect avoidance in the fault tolerant TESH networked processors analyzing the sensor array.

[1]  Susumu Horiguchi,et al.  TESH: A New Hierarchical Interconnection Network for Massively Parallel Computing , 1997 .

[2]  Israel Koren,et al.  A self-correcting active pixel camera , 2000, Proceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

[3]  Vijay K. Jain,et al.  VLSI considerations for TESH: a new hierarchical interconnection network for 3-D integration , 1998, IEEE Trans. Very Large Scale Integr. Syst..

[4]  Glenn H. Chapman,et al.  3D heterogeneous sensor system on a chip for defense and security applications , 2004, SPIE Defense + Commercial Sensing.

[5]  Israel Koren,et al.  Advanced fault-tolerance techniques for a color digital camera-on-a-chip , 2001, Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.

[6]  Vijay K. Jain,et al.  Automatic Reconfiguration and Yield of the TESH Multicomputer Network , 2002, IEEE Trans. Computers.

[7]  Andrew Clark,et al.  Commercialization of Honeywell's VCSEL technology: further developments , 2001, SPIE OPTO.

[8]  Glenn H. Chapman,et al.  Implementation and testing of fault-tolerant photodiode-based active pixel sensor (APS) , 2003, Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI Systems.

[9]  Vijay K. Jain,et al.  Yield estimates for the TESH multicomputer network , 2002, 17th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2002. DFT 2002. Proceedings..

[10]  Glenn H. Chapman,et al.  Design of a self-correcting active pixel sensor , 2001, Proceedings 2001 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.