Island-Style Monolithic Three-Dimensional CMOS-Nanoelectromechanical Logic Circuits

Island-style monolithic three-dimensional (M3D) CMOS- nanoelectromechanical (CMOS-NEM) reconfigurable logic (RL) circuits are experimentally demonstrated showing the full operation of the island-style RL: single-tile and tile-to-tile operation. For the fabrication of M3D CMOS-NEM RL circuits, 65-nm CMOS baseline process was used, in which copper NEM memory switches are integrated over the CMOS logic circuits by using dual damascene process. It is predicted that our proposed M3D CMOS-NEM RL circuits will exhibit <inline-formula> <tex-math notation="LaTeX">$4.6 \times$ </tex-math></inline-formula> higher chip density, <inline-formula> <tex-math notation="LaTeX">$2.3 \times$ </tex-math></inline-formula> higher operation frequency and <inline-formula> <tex-math notation="LaTeX">$9.3 \times$ </tex-math></inline-formula> lower power consumption than CMOS-only ones (tri-state buffer case) for tile-to-tile operation.

[1]  Chris H. Kim,et al.  A Bit-by-Bit Re-Writable Eflash in a Generic 65 nm Logic Process for Moderate-Density Nonvolatile Memory Applications , 2014, IEEE Journal of Solid-State Circuits.

[2]  Chen Dong,et al.  Architecture and performance evaluation of 3D CMOS-NEM FPGA , 2011, International Workshop on System Level Interconnect Prediction.

[3]  W. Choi,et al.  Three-Dimensional Integration of Complementary Metal-Oxide-Semiconductor-Nanoelectromechanical Hybrid Reconfigurable Circuits , 2015, IEEE Electron Device Letters.

[4]  Arantxa Uranga,et al.  CMOS-NEMS Copper Switches Monolithically Integrated Using a 65 nm CMOS Technology , 2016, Micromachines.

[5]  Woo Young Choi,et al.  Nonvolatile Nanoelectromechanical Memory Switches for Low-Power and High-Speed Field-Programmable Gate Arrays , 2015, IEEE Transactions on Electron Devices.

[6]  T. Liu,et al.  Nano-Electro-Mechanical Nonvolatile Memory (NEMory) Cell Design and Scaling , 2008, IEEE Transactions on Electron Devices.

[7]  Tsu-Jae King Liu,et al.  Design, Optimization, and Scaling of MEM Relays for Ultra-Low-Power Digital Logic , 2011, IEEE Transactions on Electron Devices.

[8]  Woo Young Choi,et al.  Monolithic Three-Dimensional 65-nm CMOS-Nanoelectromechanical Reconfigurable Logic for Sub-1.2-V Operation , 2017, IEEE Electron Device Letters.

[9]  H.-S. Philip Wong,et al.  Nano-Electro-Mechanical relays for FPGA routing: Experimental demonstration and a design technique , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[10]  H.-S. Philip Wong,et al.  Efficient FPGAs using nanoelectromechanical relays , 2010, FPGA '10.

[11]  R. Howe,et al.  Integration of nanoelectromechanical (NEM) relays with silicon CMOS with functional CMOS-NEM circuit , 2011, 2011 International Electron Devices Meeting.