LWR reduction in low-k1 ArF-immersion lithography
暂无分享,去创建一个
Daisuke Kawamura | Tetsu Kawasaki | Shinichi Ito | Hirokazu Kato | Kentaro Matsunaga | Eishi Shiobara | Mitsuaki Iwashita | Yuichiro Inatomi | Tomoya Oori
[1] Koutarou Sho,et al. Effect of post development process for resist roughness , 2005, SPIE Advanced Lithography.
[2] Jung-Hyeon Lee,et al. ArF issues of 90-nm-node DRAM device integration , 2003, SPIE Advanced Lithography.
[3] Munirathna Padmanaban,et al. Effect of hard bake process on LER , 2005, SPIE Advanced Lithography.
[4] Tetsu Kawasaki,et al. LWR reduction in ArF resist pattern by resist smoothing process , 2006, SPIE Advanced Lithography.
[5] Han-Ku Cho,et al. Effect of line-edge roughness (LER) and line-width roughness (LWR) on sub-100-nm device performance , 2004, SPIE Advanced Lithography.
[6] Kouichirou Tsujita,et al. Influence of line-edge roughness on MOSFET devices with sub-50-nm gates , 2004, SPIE Advanced Lithography.
[7] C.H. Diaz,et al. An experimentally validated analytical model for gate line-edge roughness (LER) effects on technology scaling , 2001, IEEE Electron Device Letters.
[8] William Lawrence. Spatial frequency analysis of line-edge roughness in nine chemically related photoresists , 2003, SPIE Advanced Lithography.
[9] Atsuko Yamaguchi,et al. Metrology of LER: influence of line-edge roughness (LER) on transistor performance , 2004, SPIE Advanced Lithography.
[10] Bruno M. La Fontaine,et al. Characterization of line-edge roughness in photoresist using an image fading technique , 2004, SPIE Advanced Lithography.