Minimization of Jitter in Digital Systems using Dual Phase-locked Loops

Timing jitter is a concern in high frequency timing circuits. Its presence can degrade system performance in many high-speed applications. This paper describes a new method for minimization of timing jitter using two phase-locked loops connected in cascade, where the first one has a voltage-controlled crystal oscillator to eliminate the input jitter and the second is a wide-band phase-locked loop. RMS jitter, the usual system performance criterion, is analyzed in both phase-locked loops, and results of simulations using MATLAB are presented. The methodology described is also applicable to other types of clock generator.

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