Silicon-Based Dynamic Synapse With Depressing Response

A compact implementation of a dynamic charge transfer synapse cell, capable of implementing synaptic depression, is presented. The cell is combined with a simple current mirror summing node to produce biologically plausible postsynaptic potentials (PSPs). A single charge packet is effectively transferred from the synapse to the summing node, whenever a presynaptic pulse is applied to one of its terminals. The charge packet is “weighted” by a voltage applied to the second terminal of the synapse. A voltage applied to the third terminal determines the charge recovery time in the synapse, which can be adjusted over several orders of magnitude. This voltage determines the paired pulse ratio for the synapse. The fall time of the PSP is also adjustable and is set by the gate voltage of a metal-oxide-semiconductor field-effect transistor operating in subthreshold. Results extracted from chips fabricated in a 0.35-μm complementary metal-oxide-semiconductor process, alongside theoretical and simulation results, confirm the ability of the cell to produce PSPs that are characteristic of real synapses. The concept addresses a key requirement for scalable hardware neural networks.

[1]  Mauricio Barahona,et al.  A biomimetic CMOS synapse , 2006, 2006 IEEE International Symposium on Circuits and Systems.

[2]  Piotr Dudek,et al.  Simple Analogue VLSI Circuit of a Cortical Neuron , 2006, 2006 13th IEEE International Conference on Electronics, Circuits and Systems.

[3]  Shih-Chii Liu,et al.  Temporal coding in a silicon network of integrate-and-fire neurons , 2004, IEEE Transactions on Neural Networks.

[4]  Krzysztof J. Cios,et al.  Advances in applications of spiking neuron networks , 2000, SPIE Defense + Commercial Sensing.

[5]  Steve B. Furber,et al.  Implementing Learning on the SpiNNaker Universal Neural Chip Multiprocessor , 2009, ICONIP.

[6]  A. Ayatollahi,et al.  Implementation of biologically plausible spiking neural network models on the memristor crossbar-based CMOS/nano circuits , 2009, 2009 European Conference on Circuit Theory and Design.

[7]  Peng Xu,et al.  Ultra-low Spike Rate Silicon Neuron , 2007, 2007 IEEE Biomedical Circuits and Systems Conference.

[8]  B. Katz.  Nerve, Muscle and Synapse , 1966 .

[9]  Zhou Weixiong.  A Review of the Research on Realization of Analog Neural Cells , 2002 .

[10]  Ammar Belatreche,et al.  Evaluating the training dynamics of a CMOS based synapse , 2011, The 2011 International Joint Conference on Neural Networks.

[11]  Narayan Srinivasa,et al.  Programming Time-Multiplexed Reconfigurable Hardware Using a Scalable Neuromorphic Compiler , 2012, IEEE Transactions on Neural Networks and Learning Systems.

[12]  Jan M. Rabaey,et al.  Digital Integrated Circuits: A Design Perspective , 1995 .

[13]  Miguel Figueroa,et al.  Adaptive CMOS: from biological inspiration to systems-on-a-chip , 2002, Proc. IEEE.

[14]  René Schüffny,et al.  Analyzing the Scaling of Connectivity in Neuromorphic Hardware and in Models of Neural Networks , 2011, IEEE Transactions on Neural Networks.

[15]  Yannick Bornat,et al.  Analog-digital simulations of full conductance-based networks of spiking neurons with spike timing dependent plasticity , 2006, Network.

[16]  Alan F. Murray,et al.  Large Developing Receptive Fields Using a Distributed and Locally Reprogrammable Address–Event Receiver , 2010, IEEE Transactions on Neural Networks.

[17]  Simon R. Schultz,et al.  Analogue VLSI 'integrate-and-fire' neuron with frequency adaptation , 1995 .

[18]  H. Markram,et al.  The neural code between neocortical pyramidal neurons depends on neurotransmitter release probability. , 1997, Proceedings of the National Academy of Sciences of the United States of America.

[19]  Jacques Gautrais,et al.  SpikeNET: A simulator for modeling large networks of integrate and fire neurons , 1999, Neurocomputing.

[20]  Liam McDaid,et al.  A Reconfigurable and Biologically Inspired Paradigm for Computation Using Network-On-Chip and Spiking Neural Networks , 2009, Int. J. Reconfigurable Comput..

[21]  Stephen B. Furber,et al.  Virtual synaptic interconnect using an asynchronous network-on-chip , 2008, 2008 IEEE International Joint Conference on Neural Networks (IEEE World Congress on Computational Intelligence).

[22]  Michael A. Arbib,et al.  The handbook of brain theory and neural networks , 1995, A Bradford book.

[23]  Chiara Bartolozzi,et al.  Synaptic Dynamics in Analog VLSI , 2007, Neural Computation.

[24]  Richard H. R. Hahnloser,et al.  Silicon synaptic depression , 2001, Biological Cybernetics.

[25]  Michael L. Hines,et al.  Parallel network simulations with NEURON , 2006, Journal of Computational Neuroscience.

[26]  H. Markram,et al.  Potential for multiple mechanisms, phenomena and algorithms for synaptic plasticity at single synapses , 1998, Neuropharmacology.

[27]  Kwabena Boahen,et al.  The Retinomorphic Approach: Pixel-Parallel Adaptive Amplification, Filtering, and Quantization , 1997 .

[28]  C. Diorio.  A p-channel MOS synapse transistor with self-convergent memory writes , 2000 .

[29]  Vittorio Dante,et al.  A VLSI recurrent network of integrate-and-fire neurons connected by plastic synapses with long-term memory , 2003, IEEE Trans. Neural Networks.

[30]  Carver A. Mead,et al.  A single-transistor silicon synapse , 1996 .

[31]  Nicholas T. Carnevale,et al.  Simulation of networks of spiking neurons: A review of tools and strategies , 2006, Journal of Computational Neuroscience.

[32]  Yannick Bornat,et al.  Design of a modular and mixed neuromimetic ASIC , 2006, 2006 13th IEEE International Conference on Electronics, Circuits and Systems.

[33]  René Schüffny,et al.  Synapse dynamics in CMOS derived from a model of neurotransmitter release , 2011, 2011 20th European Conference on Circuit Theory and Design (ECCTD).

[34]  Howard C. Card,et al.  Hebbian plasticity in MOS synapses , 1991 .

[35]  Jerzy B. Lont.  Analog CMOS implementation of a multi-layer perceptron with nonlinear synapses , 1992, IEEE Trans. Neural Networks.

[36]  Robert J. Butera,et al.  An artificial synapse for interfacing to biological neurons , 2006, 2006 IEEE International Symposium on Circuits and Systems.

[37]  Giacomo Indiveri,et al.  An adaptive silicon synapse , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

[38]  B. A. Minch,et al.  A floating-gate MOS learning array with locally computed weight updates , 1997 .

[39]  Shih-Chii Liu,et al.  Modeling Short-Term Synaptic Depression in Silicon , 2003, Neural Computation.

[40]  Henry Markram,et al.  Neural Networks with Dynamic Synapses , 1998, Neural Computation.

[41]  Giacomo Indiveri,et al.  A VLSI spike-driven dynamic synapse which learns only when necessary , 2006, 2006 IEEE International Symposium on Circuits and Systems.

[42]  Alan F. Murray,et al.  The Prospects for Analogue Neural VLSI , 1997, Int. J. Neural Syst..

[43]  Giacomo Indiveri,et al.  A VLSI array of low-power spiking neurons and bistable synapses with spike-timing dependent plasticity , 2006, IEEE Transactions on Neural Networks.

[44]  Tobi Delbrück,et al.  Orientation-Selective aVLSI Spiking Neurons , 2001, NIPS.

[45]  Yannick Bornat,et al.  Neuromimetic ICs with analog cores: an alternative for simulating spiking neural networks , 2007, 2007 IEEE International Symposium on Circuits and Systems.

[46]  Tyson S. Hall,et al.  Automatic rapid programming of large arrays of floating-gate elements , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[47]  Hilbert J. Kappen,et al.  On the role of dynamical synapses in coincidence detection , 2001, Neurocomputing.