A broadband packet switch architecture with input and output queueing

The ATM is one of the most promising solutions for B-ISDN. Switch architectures based on Batcher-banyan networks are considered the most suitable for constructing large-dimension broadband packet switches. Though the Batcher-banyan network is internally nonblocking, the ubiquitous problem of packet loss resulting from outlet conflict can only be reduced by external buffering. Buffering strategies are basically categorized into two classes: input buffering and output buffering. For input-buffered switches, a phenomenon called head-of-the-line (HOL) blocking limits the maximum throughput to only 58.6 percent (2-/spl radic/2). On the other hand, output buffering achieves much higher throughput, but the entire switch has to be operated at a sufficiently high speed in order to deliver all the packets simultaneously destined for the same outlet. This generally imposes severe implementation problems. We propose a switch architecture with combined input and output queueing. The switch fabric consists of a Batcher sorting network, a radix-r shuffle mapping network, and r parallel distributing modules. The input queues and the switch fabric run at the same speed as the input and output trunks. However, up to r packets may arrive at an output queue in a single time slot. We analyze the throughput-delay characteristics of the proposed switch. The maximum throughput in the case where r=2 is 88.6 percent. For r=4, the proposed switch offers a 99.6 percent maximum throughput. In addition, the proposed switch relieves the HOL blocking by allowing up to r packets to be delivered to the same outlet in one time slot. Consequently, the average delay is also reduced.