A highly efficient external memory interface architecture for AVS HD video encoder
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Wen Gao | Lei Zhang | Huizhu Jia | Xiaofeng Huang | Don Xie | Chuang Zhu | Kaijin Wei
[1] Alexandru Nicolau,et al. High-Level synthesis with Synchronous and RAMBUS DRAMs , 1998 .
[2] Wen Gao,et al. An Optimized Hardware Video Encoder for AVS with Level C+ Data Reuse Scheme for Motion Estimation , 2012, 2012 IEEE International Conference on Multimedia and Expo.
[3] Madhukar Budagavi,et al. Memory Bandwidth and Power Reduction Using Lossy Reference Frame Compression in Video Encoding , 2011, IEEE Transactions on Circuits and Systems for Video Technology.
[4] Hai Bing Yin,et al. A highly efficient pipeline architecture of RDO-based mode decision design for AVS HD video encoder , 2011, 2011 IEEE International Conference on Multimedia and Expo.
[5] William J. Dally,et al. Memory access scheduling , 2000, Proceedings of 27th International Symposium on Computer Architecture (IEEE Cat. No.RS00201).
[6] In-Cheol Park,et al. High-performance and low-power memory-interface architecture for video processing applications , 2001, IEEE Trans. Circuits Syst. Video Technol..
[7] Chein-Wei Jen,et al. An efficient quality-aware memory controller for multimedia platform SoC , 2005, IEEE Transactions on Circuits and Systems for Video Technology.
[8] Wen Gao,et al. A flexible and high-performance hardware video encoder architecture , 2012, 2012 Picture Coding Symposium.
[9] Hiroshi Ueda,et al. A 342 mW Mobile Application Processor With Full-HD Multi-Standard Video Codec and Tile-Based Address-Translation Circuits , 2010, IEEE Journal of Solid-State Circuits.
[10] Wen Gao,et al. AVS Video Coding Standard , 2010, Intelligent Multimedia Communication.