A novel FPGA local interconnect test scheme and automatic TC derivation/generation

This paper presents a novel local interconnect testing scheme for field programmable gate arrays (FPGAs). To maximize parallel testing, error-detecting code is used for testing one portion of interconnects and functional test of D latch for another in a test configuration (TC). A polynomial run time algorithm is introduced for deriving a minimal set of TCs. An in-house CAD tool is developed to automate the generation of device configurations from the set of TCs.

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