An approach to build cycle accurate full system VLIW simulation platform

Abstract Very long instruction word (VLIW) architecture is widely used in the design of digital signal processors (DSPs) and application-specific processors because of its hardware simplicity and high efficiency. Some heterogeneous systems also use VLIW style accelerators to achieve high computing performance and power efficiency. However, there are few widely accepted simulators that can cycle-accurately model a VLIW architecture or simulate the entire heterogeneous system with VLIW accelerators. In this paper we present an approach to build cycle accurate full system VLIW simulation platform. The basic idea is to analyze Petri Nets modeling used in the traditional cycle accurate simulation and adjust it to match VLIW architecture. The adjustments reconstruct and optimize the colored token, the place and the arc in Petri Nets in order to adapt it with VLIW characteristics. According to our approach and based on the InOrder simulator in the open source simulator framework Gem5, we build a heterogeneous multicore full system simulator for the MaPU (Mathematical Processor Unit) chip, which is composed by a functional accurate ARM simulator and a cycle accurate accelerator simulator. To evaluate the performance and accuracy of our simulator ‘Gem5-MaPU’, we compare the results of a set of DSP benchmarks executed by both the simulator and the RTL model. The result shows our simulator is about 1000 times faster than the RTL model while the cycle error is reduced to less than 5%. With high accuracy rate and good accelerating ratio over RTL simulation, the cycle accurate simulator turns out to be an efficient and flexible tool for VLIW related architectures’ study and development, such as the hardware-software co-design and performance evaluation, etc.