Forensic engineering techniques for VLSI CAD tools

The proliferation of the Internet has affected the business model of almost all semiconductor and VLSI CAD companies that rely on intellectual property (IP) as their main source of revenues. The fact that IP has become more accessible and easily transferable, has influenced the emergence of copyright infringement as one of the most common obstructions to e-commerce of IP. In this paper, we propose a generic forensic engineering technique that addresses a number of copyright infringement scenarios. Given a solution <italic>S<subscrpt>P</subscrpt></italic> to a particular optimization problem instance <italic>P</italic> and a finite set of algorithms <italic>A</italic> applicable to <italic>P</italic>, the goal is to identify with a certain degree of confidence the algorithm <italic>A<subscrpt>i</subscrpt></italic> which has been applied to <italic>P</italic> in order to obtain <italic>S<subscrpt>P</subscrpt></italic>. We have applied forensic analysis principles to two problem instances commonly encountered in VLSI CAD: graph coloring and boolean satisfiability. We have demonstrated that solutions produced by strategically different algorithms can be associated with their corresponding algorithms with high accuracy.

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