Module assignment for low power

We investigate the problem of minimizing the total power consumption during the binding of operations to functional units in a scheduled data path with functional pipelining and conditional branching for data intensive applications. We first present a technique to estimate the power consumption in a functionally pipelined data path and then formulate the power optimization problem as a max cost multi commodity flow problem and solve it optimally. Our proposed method can augment most high level synthesis algorithms as a post processing step for reducing power after the optimizations for area or speed have been completed. An average power savings of 28% has been observed after we apply our method to pipelined designs that have been optimized using conventional techniques.

[1]  Paul M. Chau,et al.  A high-level synthesis methodology for low-power VLSI design , 1994, Proceedings of 1994 IEEE Symposium on Low Power Electronics.

[2]  D. A. Bell,et al.  Information Theory and Reliable Communication , 1969 .

[3]  Miodrag Potkonjak,et al.  HYPER-LP: a system for power minimization using architectural transformations , 1992, ICCAD.

[4]  Minh N. Do,et al.  Youn-Long Steve Lin , 1992 .

[5]  Fadi J. Kurdahi,et al.  REAL: A Program for REgister ALlocation , 1987, 24th ACM/IEEE Design Automation Conference.

[6]  Alice C. Parker,et al.  Sehwa: a software package for synthesis of pipelines from behavioral specifications , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[7]  Sidney C. Port,et al.  Probability, Random Variables, and Stochastic Processes—Second Edition (Athanasios Papoulis) , 1986 .

[8]  Miodrag Potkonjak,et al.  HYPER-LP: a system for power minimization using architectural transformations , 1992, ICCAD 1992.

[9]  Leon Stok,et al.  Architectural synthesis and optimization of digital systems , 1991 .

[10]  Katta G. Murty,et al.  Network programming , 1992 .

[11]  J. Rabaey,et al.  Behavioral Level Power Estimation and Exploration , 1997 .

[12]  Niraj K. Jha,et al.  Behavioral synthesis for low power , 1994, Proceedings 1994 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[13]  Catherine H. Gebotys,et al.  Optimal VLSI Architectural Synthesis , 1992 .

[14]  Daniel D. Gajski,et al.  High ― Level Synthesis: Introduction to Chip and System Design , 1992 .

[15]  Bruno O. Shubert,et al.  Random variables and stochastic processes , 1979 .

[16]  Massoud Pedram,et al.  Register Allocation and Binding for Low Power , 1995, 32nd Design Automation Conference.

[17]  Catherine H. Gebotys,et al.  Optimal VLSI Architectural Synthesis: Area, Performance and Testability , 1991 .

[18]  Giovanni De Micheli,et al.  Synthesis and Optimization of Digital Circuits , 1994 .

[19]  G. G. Stokes.  "J." , 1890, The New Yale Book of Quotations.

[20]  Steve Rogers,et al.  Adaptive Filter Theory , 1996 .

[21]  Thomas Lengauer,et al.  Combinatorial algorithms for integrated circuit layout , 1990, Applicable theory in computer science.

[22]  P. M. Chau,et al.  A model for estimating power dissipation in a class of DSP VLSI chips , 1991 .

[23]  Wayne Wolf,et al.  High-Level VLSI Synthesis , 1991 .

[24]  Andrew J. Viterbi,et al.  Principles of Digital Communication and Coding , 1979 .

[25]  Ping Yang,et al.  A Monte Carlo approach for power estimation , 1993, IEEE Trans. Very Large Scale Integr. Syst..