A convex programming approach to problems in VLSI design

Two problems in VLSI CAD, namely, those of transistor sizing and design centering, are dealt with in this thesis. The transistor sizing problem is described as follows. A general sequential circuit consists of a number of combinational stages that lie between latches. For the circuit to meet a given clocking specification, it is necessary for each combinational stage to satisfy certain delay requirements. Roughly speaking, increasing the sizes of some transistors in a stage reduces the delay, with the penalty of increased area. The problem of transistor sizing is to minimize the area of a combinational stage, subject to its delay being less than a given specification. The problem is formulated as a convex programming problem. An efficient convex optimization algorithm, in conjunction with an improved timing analysis method, is used to solve this problem. The design centering problem is an important issue in design for manufacturability. In the face of manufacturing process variations, the values of design parameters may be perturbed from the nominal values, due to which a circuit may not satisfy the behavioral specifications that it was designed for. The idea of design centering is to choose the nominal values so as to allow maximal perturbations during manufacturing, while continuing to satisfy behavioral specifications. The procedure that is outlined in this thesis consists of two steps: efficient approximation of the feasible region by a polytope, and finding the design center. For the latter step, two algorithms are outlined. The first algorithm finds the largest Hessian ellipsoid which can be inscribed in the polytope, while the second formulates the design centering problem as a convex programming problem.