A 3.5–6.8-GHz Wide-Bandwidth DTC-Assisted Fractional-N All-Digital PLL With a MASH $\Delta \Sigma $ -TDC for Low In-Band Phase Noise

This paper proposes a digital-to-time converter (DTC)-assisted fractional-N wide-bandwidth all-digital phase-locked loop (ADPLL) with a fine-resolution time-to-digital converter (TDC). The TDC employs a two-channel time-interleaved time-domain register with an implicit adder/subtractor realizing an error-feedback topology. Such an error-feedback unit of a first-order <inline-formula> <tex-math notation="LaTeX">$\Delta \Sigma $ </tex-math></inline-formula>-TDC can be cascaded as a multi-stage noise shaping configuration to achieve higher-order noise-shaping and, thereby, low in-band phase noise (PN) of the ADPLL. A digitally controlled oscillator with a transformer and a pair of cross-coupled NMOS amplifiers exploits magnetic and capacitive coupling to achieve nearly an octave frequency coverage, i.e., 1.73–3.38 GHz (after a <inline-formula> <tex-math notation="LaTeX">$\div $ </tex-math></inline-formula>2 division). Fabricated in 40-nm CMOS, the ADPLL achieves better than −110-dBc/Hz in-band PN and occupies an active area of 0.5 mm<sup>2</sup>. With a 50-MHz reference clock, a 2-GHz output RF clock, and a loop bandwidth of 800 kHz, this prototype achieves 420-fs<inline-formula> <tex-math notation="LaTeX">$_{{\mathrm{rms}}}$ </tex-math></inline-formula> jitter, integrated from 1-kHz to 30-MHz offset, while drawing 10.7 mW.

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