A low jitter arbitrary-input pulsewidth control loop with wide duty cycle adjustment

An arbitrary-input pulsewidth control loop (AIPWCL) based on a delay-locked loop with duty cycle corrector is presented. The duty cycles of the clock signals can be adjusted from 10% to 90% in 10% steps. The proposed AIPWCL is designed and simulated by using tsmc 0.13µm CMOS process. The operation frequency range is from 770MHz to 1.05GHz. The locking time of AIPWCL is less than 40ns within the operation frequency band. The power dissipation is 4.38mW at 1.2V voltage supply. The peak-to-peak jitter is less than 1ps at an input clock frequency of 1GHz while adjusting various duty cycles.

[1]  Shen-Iuan Liu,et al.  A wide-range delay-locked loop with a fixed latency of one clock cycle , 2002, IEEE J. Solid State Circuits.

[2]  Kuo-Hsing Cheng,et al.  A High Linearity, Fast-Locking Pulsewidth Control Loop With Digitally Programmable Duty Cycle Correction for Wide Range Operation , 2008, IEEE Journal of Solid-State Circuits.

[3]  Jinn-Shyan Wang,et al.  Low-voltage pulsewidth control loops for SOC applications , 2002 .

[4]  Shu-Ming Chang,et al.  A 2.2 GHz programmable DLL-based frequency multiplier for SOC applications , 2004, Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits.

[5]  Shen-Iuan Liu,et al.  A single-path pulsewidth control loop with a built-in delay-locked loop , 2005, IEEE Journal of Solid-State Circuits.

[6]  Shen-Iuan Liu,et al.  All-digital delay-locked loop/pulsewidth-control loop with adjustable duty cycles , 2006 .

[7]  Hong-Yi Huang,et al.  Low-power 50% duty cycle corrector , 2008, 2008 IEEE International Symposium on Circuits and Systems.

[8]  Fenghao Mu,et al.  Pulsewidth control loop in high-speed CMOS clock buffers , 2000, IEEE Journal of Solid-State Circuits.