Low Power Computing Paradigms Based on Emerging Non-Volatile Nanodevices

[1]  Jacques-Olivier Klein,et al.  Robust neural logic block (NLB) based on memristor crossbar array , 2011, 2011 IEEE/ACM International Symposium on Nanoscale Architectures.

[2]  Eric Belhaire,et al.  CMOS/Magnetic Hybrid Architectures , 2007, 2007 14th IEEE International Conference on Electronics, Circuits and Systems.

[3]  D. Stewart,et al.  The missing memristor found , 2008, Nature.

[4]  R. Ramesh,et al.  Epitaxial BiFeO3 Multiferroic Thin Film Heterostructures , 2003, Science.

[5]  John W. Backus,et al.  Can programming be liberated from the von Neumann style?: a functional style and its algebra of programs , 1978, CACM.

[6]  Weisheng Zhao,et al.  Electrical Modeling of Stochastic Spin Transfer Torque Writing in Magnetic Tunnel Junctions for Memory and Logic Applications , 2013, IEEE Transactions on Magnetics.

[7]  Gregory S. Snider,et al.  Spike-timing-dependent learning in memristive nanodevices , 2008, 2008 IEEE International Symposium on Nanoscale Architectures.

[8]  A. Fert,et al.  The emergence of spin electronics in data storage. , 2007, Nature materials.

[9]  Hai Helen Li,et al.  Spintronic Memristor Through Spin-Torque-Induced Magnetization Motion , 2009, IEEE Electron Device Letters.

[10]  Gregory S. Snider,et al.  ‘Memristive’ switches enable ‘stateful’ logic operations via material implication , 2010, Nature.

[11]  Eric Belhaire,et al.  TAS-MRAM-Based Low-Power High-Speed Runtime Reconfiguration (RTR) FPGA , 2009, TRETS.

[12]  Youguang Zhang,et al.  Spintronics for low-power computing , 2014, 2014 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[13]  Mircea R. Stan,et al.  RAMA: a self-assembled multiferroic magnetic QCA for low power systems , 2011, GLSVLSI '11.

[14]  Jacques-Olivier Klein,et al.  Racetrack memory based reconfigurable computing , 2013, 2013 IEEE Faible Tension Faible Consommation.

[15]  J. Scott,et al.  Data storage. Multiferroic memories. , 2007, Nature materials.

[16]  Jacques-Olivier Klein,et al.  Magnetic Adder Based on Racetrack Memory , 2013, IEEE Transactions on Circuits and Systems I: Regular Papers.

[17]  Jacques-Olivier Klein,et al.  Design and Modeling of a Neuro-Inspired Learning Circuit Using Nanotube-Based Memory Devices , 2011, IEEE Transactions on Circuits and Systems I: Regular Papers.

[18]  G. Bi,et al.  Synaptic modification by correlated activity: Hebb's postulate revisited. , 2001, Annual review of neuroscience.

[19]  Eric Belhaire,et al.  New non‐volatile logic based on spin‐MTJ , 2008 .

[20]  D. Strukov,et al.  CMOL FPGA: a reconfigurable architecture for hybrid digital circuits with two-terminal nanodevices , 2005 .

[21]  Eric Belhaire,et al.  Spin transfer torque (STT)-MRAM--based runtime reconfiguration FPGA circuit , 2009, TECS.

[22]  Fabien Alibart,et al.  Pavlov's Dog Associative Learning Demonstrated on Synaptic-Like Organic Transistors , 2013, Neural Computation.

[23]  Lionel Torres,et al.  High Performance SoC Design Using Magnetic Logic and Memory , 2011, VLSI-SoC.

[24]  C. Binek,et al.  Magnetoelectronics with magnetoelectrics , 2005 .

[25]  Zhaohao Wang,et al.  Spin-electronics based logic fabrics , 2013, 2013 IFIP/IEEE 21st International Conference on Very Large Scale Integration (VLSI-SoC).

[26]  Carver A. Mead,et al.  Neuromorphic electronic systems , 1990, Proc. IEEE.

[27]  Massimiliano Di Ventra,et al.  Neuromorphic, Digital, and Quantum Computation With Memory Circuit Elements , 2010, Proceedings of the IEEE.

[28]  Jacques-Olivier Klein,et al.  Low power, high reliability magnetic flip-flop , 2010 .

[29]  A. Fert,et al.  Tunnel junctions with multiferroic barriers. , 2007, Nature materials.

[30]  C. Gamrat,et al.  Nanotube devices based crossbar architecture: toward neuromorphic computing , 2010, Nanotechnology.

[31]  J. Grollier,et al.  A ferroelectric memristor. , 2012, Nature materials.

[32]  D. Panescu,et al.  Emerging Technologies , 2008, IEEE Engineering in Medicine and Biology Magazine.

[33]  Weisheng Zhao,et al.  Perpendicular-magnetic-anisotropy CoFeB racetrack memory , 2012 .

[34]  Vikram Bhatt,et al.  The GreenDroid Mobile Application Processor: An Architecture for Silicon's Dark Future , 2011, IEEE Micro.

[35]  Jacques-Olivier Klein,et al.  Nanodevice-based novel computing paradigms and the neuromorphic approach , 2012, 2012 IEEE International Symposium on Circuits and Systems.

[36]  André DeHon,et al.  Array-based architecture for FET-based, nanoscale electronics , 2003 .

[37]  Weisheng Zhao,et al.  Domain Wall Shift Register-Based Reconfigurable Logic , 2011, IEEE Transactions on Magnetics.

[38]  Zhaohao Wang,et al.  A low-cost built-in error correction circuit design for STT-MRAM reliability improvement , 2013, Microelectron. Reliab..

[39]  L. Chua.  Memristor-The missing circuit element , 1971 .

[40]  Jean Michel Portal,et al.  Non-Volatile Flip-Flop Based on Unipolar ReRAM for Power-Down Applications , 2012, J. Low Power Electron..

[41]  H. Noguchi,et al.  Progress of STT-MRAM technology and the effect on normally-off computing systems , 2012, 2012 International Electron Devices Meeting.

[42]  Yiran Chen,et al.  Low-power dual-element memristor based memory design , 2010, 2010 ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED).

[43]  Yiran Chen,et al.  Design Margin Exploration of Spin-Transfer Torque RAM (STT-RAM) in Scaled Technologies , 2010, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[44]  Mahmut T. Kandemir,et al.  Leakage Current: Moore's Law Meets Static Power , 2003, Computer.

[45]  Siddhartha Bhargava,et al.  Architecture, Design and Development of a Green ICT System , 2011 .

[46]  P. Chow,et al.  The design of an SRAM-based field-programmable gate array. I. Architecture , 1999, IEEE Trans. Very Large Scale Integr. Syst..