Synchronous mirror delay circuit

The present invention relates to a synchronous mirror delay circuit. The present invention provides an output buffer circuit comprising: an output buffer for delaying an external clock by a first delay time to output a first internal clock; a delay monitoring circuit for delaying the first internal clock by a second delay time; And a n-th unit delay unit (n2) for delaying the output of the delay monitoring circuit to a third delay time; and a mirror control unit for inverting the output of the forward delay array in response to the first internal clock And a first delay unit for delaying the output of the mirror delay circuit by a first delay time and a second delay unit for delaying the output of the second delay unit by a third delay time, And outputting a second internal clock by delaying the first internal clock by a fourth delay time. Therefore, the present invention requires a small number of unit delay elements to generate an internal clock that is locked to a low frequency, i.e., an external clock having a long cycle, and thus the layout area can be reduced.