A history model for managing the VLSI design process

A history model is proposed to support the dynamic aspects of VLSI design, i.e., the controlled and disciplined sequencing of CAD tool invocations. This model is based on a task specification language, for encapsulating CAD tool invocations, and a novel activity thread, which maintains the history of task invocations and serves as a focus for sharing work results in a cooperative manner. A prototype was built on top of the OCT CAD framework.<<ETX>>

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