Synchronous Sequential Machines: A Modular and Testable Design

It will be shown that a single-input n-definite machine realized by a universal modular tree, in which each module consists of AND-EXCLUSIVE-OR-DELAY (AND-EOR-DELAY) as a basic element, can be tested for single stuck-type-faults by tests of length 2n + 3 only. This is a marked improvement over the previous results for trees consisting of AND-OR-DELAYS, which are known to have test lengths of exponential growth.

[1]  Thomas F. Arnold.  R70-21 Time and Tape Complexity of Pushdown Automaton Languages , 1970, IEEE Transactions on Computers.

[2]  Arthur D. Friedman.  Feedback in Asynchronous Sequential Circuits , 1966, IEEE Trans. Electron. Comput..

[3]  SUDHAKAR M. REDDY,et al.  Easily Testable Realizations ror Logic Functions , 1972, IEEE Transactions on Computers.

[4]  Arthur D. Friedman.  Feedback in Synchronous Sequential Switching Circuits , 1966, IEEE Trans. Electron. Comput..

[5]  Herschel H. Loomis,et al.  High Rate Realization of Finite-State Machines , 1975, IEEE Transactions on Computers.

[6]  Monty Newborn.  A Synthesis Technique for Binary Input-Binary Output Synchronous Sequential Moore Machines , 1968, IEEE Transactions on Computers.

[7]  Edward P. Hsieh,et al.  Uniform modular realization of sequential machines , 1968, ACM National Conference.

[8]  Monty Newborn,et al.  Iteratively Realized Sequential Circuits , 1970, IEEE Transactions on Computers.

[9]  Sudhakar M. Reddy,et al.  Easily Testable Two-Dimensional Cellular Logic Arrays , 1974, IEEE Transactions on Computers.

[10]  Richard A. Thompson,et al.  Diagnosis of Faults in Modular Trees , 1979, IEEE Transactions on Computers.

[11]  Richard A. Thompson,et al.  Universal Modular Trees: A Design Procedure , 1978, IEEE Transactions on Computers.

[12]  John P. Hayes,et al.  Transition Count Testing of Combinational Logic Circuits , 1976, IEEE Transactions on Computers.