Experimental Studies on SMT-based Debugging

SAT-based debugging is a method to automate the debugging process that works quite well on the Boolean level. But on circuits with large arithmetic structures the underlying SAT solver – a Boolean proof engine – often does not finish within the required resource limits. Thus, new solving techniques are required to overcome the gap. Solvers for Satisfiability Modulo Theory (SMT) provide a higher level of abstraction by combining SAT with theory solvers on the word level. This allows compact handling of many hardware components. In this work we focus on debugging with SMT, i.e. SMTbased debugging. An evaluation on combinational and sequential models on RTL is given. For more than 90% of the instances our experimental studies show significant run time improvements of SMT-based debugging over SATbased debugging.

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