Safe limits on voltage reduction efficiency in GPUs: A direct measurement approach
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Pradip Bose | Jingwen Leng | Vijay Janapa Reddi | Alper Buyuktosunoglu | Ramon Bertran Monfort | V. Reddi | A. Buyuktosunoglu | P. Bose | Jingwen Leng
[1] Vivek Tiwari,et al. Microarchitectural simulation and control of di/dt-induced power supply voltage variation , 2002, Proceedings Eighth International Symposium on High Performance Computer Architecture.
[2] Kevin Skadron,et al. Rodinia: A benchmark suite for heterogeneous computing , 2009, 2009 IEEE International Symposium on Workload Characterization (IISWC).
[3] Cristian Constantinescu,et al. Silent Data Corruption - Myth or reality? , 2008, DSN.
[4] Margaret Martonosi,et al. Control techniques to eliminate voltage emergencies in high performance processors , 2003, The Ninth International Symposium on High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings..
[5] Jingwen Leng,et al. GPU voltage noise: Characterization and hierarchical smoothing of spatial and temporal voltage noise interference in GPU architectures , 2015, 2015 IEEE 21st International Symposium on High Performance Computer Architecture (HPCA).
[6] Bishop Brock,et al. Active management of timing guardband to save energy in POWER7 , 2011, 2011 44th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).
[7] Hidetoshi Onodera,et al. Statistical Parameter Extraction for Intra- and Inter-Chip Variabilities of Metal-Oxide-Semiconductor Field-Effect Transistor Characteristics , 2005 .
[8] Michael D. Smith,et al. Voltage Smoothing: Characterizing and Mitigating Voltage Noise in Production Processors via Software-Guided Thread Scheduling , 2010, 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture.
[9] Trevor Mudge,et al. Razor: a low-power pipeline based on circuit-level timing speculation , 2003, Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36..
[10] M.D. Powell,et al. Pipeline damping: a microarchitectural technique to reduce inductive noise in supply voltage , 2003, 30th Annual International Symposium on Computer Architecture, 2003. Proceedings..
[11] Nam Sung Kim,et al. GPUWattch: enabling energy optimizations in GPGPUs , 2013, ISCA.
[12] Radu Teodorescu,et al. Dynamic reduction of voltage margins by leveraging on-chip ECC in Itanium II processors , 2013, ISCA.
[13] Chenming Hu,et al. Characterization of spatial intrafield gate CD variability, its impact on circuit performance, and spatial mask-level correction , 2004, IEEE Transactions on Semiconductor Manufacturing.
[14] Pradip Bose,et al. Voltage Noise in Multi-Core Processors: Empirical Characterization and Optimization Opportunities , 2014, 2014 47th Annual IEEE/ACM International Symposium on Microarchitecture.
[15] P.J. Restle,et al. Timing uncertainty measurements on the Power5 microprocessor , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).
[16] Radu Teodorescu,et al. Using ECC Feedback to Guide Voltage Speculation in Low-Voltage Processors , 2014, 2014 47th Annual IEEE/ACM International Symposium on Microarchitecture.
[17] Soraya Ghiasi,et al. A Distributed Critical-Path Timing Monitor for a 65nm High-Performance Microprocessor , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
[18] Keshav Pingali,et al. A quantitative study of irregular programs on GPUs , 2012, 2012 IEEE International Symposium on Workload Characterization (IISWC).
[19] Keith A. Jenkins,et al. Long-term NBTI degradation under real-use conditions in IBM microprocessors , 2014, Microelectron. Reliab..
[20] William V. Huott,et al. On-chip Timing Uncertainty Measurements on IBM Microprocessors , 2008, 2008 IEEE International Test Conference.
[21] Xiang Pan,et al. VRSync: Characterizing and eliminating synchronization-induced voltage emergencies in many-core processors , 2012, 2012 39th Annual International Symposium on Computer Architecture (ISCA).
[22] Meeta Sharma Gupta,et al. GPUVolt: Modeling and characterizing voltage noise in GPU architectures , 2014, 2014 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED).
[23] Witold R. Rudnicki,et al. Feature Selection with the Boruta Package , 2010 .
[24] A. Asenov,et al. Where Do the Dopants Go? , 2005, Science.
[25] Lizy Kurian John,et al. AUDIT: Stress Testing the Automatic Way , 2012, 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture.
[26] Meeta Sharma Gupta,et al. Understanding Voltage Variations in Chip Multiprocessors using a Distributed Power-Delivery Network , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.
[27] Mattan Erez,et al. A locality-aware memory hierarchy for energy-efficient GPU architectures , 2013, 2013 46th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).
[28] Jack J. Purdum,et al. C programming guide , 1983 .
[29] Pradip Bose,et al. Abstraction and microarchitecture scaling in early-stage power modeling , 2011, 2011 IEEE 17th International Symposium on High Performance Computer Architecture.
[30] T. N. Vijaykumar,et al. Pipeline muffling and a priori current ramping: architectural techniques to reduce high-frequency inductive noise , 2003, Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003. ISLPED '03..
[31] Yu Cao,et al. Modeling of intra-die process variations for accurate analysis and optimization of nano-scale circuits , 2006, 2006 43rd ACM/IEEE Design Automation Conference.
[32] Meeta Sharma Gupta,et al. Predicting Voltage Droops Using Recurring Program and Microarchitectural Event Activity , 2010, IEEE Micro.