A 15.8 pJ/bit/iter quasi-cyclic LDPC decoder for IEEE 802.11n in 90 nm CMOS

We present a low-power quasi-cyclic (QC) low density parity check (LDPC) decoder that meets the throughput requirements of the highest-rate (600 Mbps) modes of the IEEE 802.11n WLAN standard. The design is based on the layered offset-min-sum algorithm and is runtime-programmable to process different code matrices (including all rates and block lengths specified by IEEE 802.11η). The register-transfer-level implementation has been optimized for best energy efficiency. The corresponding 90 nm CMOS ASIC has a core area of 1.77 mm2 and achieves a maximum throughput of 680 Mbps at 346 MHz clock frequency and 10 decoding iterations. The measured energy efficiency is 15.8pJ/bit/iteration at a nominal operating voltage of 1.0 V.

[1]  Alan N. Willson,et al.  A flexible decoder IC for WiMAX QC-LDPC codes , 2008, 2008 IEEE Custom Integrated Circuits Conference.

[2]  S. Litsyn,et al.  An efficient message-passing schedule for LDPC decoding , 2004, 2004 23rd IEEE Convention of Electrical and Electronics Engineers in Israel.

[3]  Joseph R. Cavallaro,et al.  A low-power 1-Gbps reconfigurable LDPC decoder design for multiple 4G wireless standards , 2008, 2008 IEEE International SOC Conference.

[4]  A. Burg,et al.  Towards generic low-power area-efficient standard cell based memory architectures , 2010, 2010 53rd IEEE International Midwest Symposium on Circuits and Systems.

[5]  Ajay Dholakia,et al.  Reduced-complexity decoding of LDPC codes , 2005, IEEE Transactions on Communications.

[6]  Robert G. Gallager,et al.  Low-density parity-check codes , 1962, IRE Trans. Inf. Theory.

[7]  Xin-Yu Shih,et al.  A real-time programmable LDPC decoder chip for arbitrary QC-LDPC parity check matrices , 2009, 2009 IEEE Asian Solid-State Circuits Conference.

[8]  A. Burg,et al.  Configurable high-throughput decoder architecture for quasi-cyclic LDPC codes , 2008, 2008 42nd Asilomar Conference on Signals, Systems and Computers.