Hybrid Fault Simulation for Synchronous Sequential Circuits

We present a fault simulator for synchronous sequential circuits that combines the efficiency of three-valued logic simulation with the exactness of a symbolic approach. The simulator is hybrid in the sense that three different modes of operation—three-valued, symbolic and mixed—are supported. We demonstrate how an automatic switching between the modes depending on the computational resources and the properties of the circuit under test can be realized, thus trading off time/space for accuracy of the computation. Furthermore, besides the usual Single Observation Time Test Strategy (SOT) for the evaluation of the fault coverage, the simulator supports evaluation according to the more general Multiple Observation Time Test Strategy (MOT). Numerous experiments are given to demonstrate the feasibility and efficiency of our approach. In particular, it is shown that, at the expense of a reasonable time penalty, the exactness of the fault coverage computation can be improved even for the largest benchmark functions.

[1]  Daniel G. Saab,et al.  CRIS: a test cultivation program for sequential VLSI circuits , 1992, ICCAD.

[2]  Melvin A. Breuer,et al.  Digital systems testing and testable design , 1990 .

[3]  Janak H. Patel,et al.  New Techniques for Deterministic Test Pattern Generation , 1999, J. Electron. Test..

[4]  David Bryan,et al.  Combinational profiles of sequential benchmark circuits , 1989, IEEE International Symposium on Circuits and Systems,.

[5]  Irith Pomeranz,et al.  Fault simulation under the multiple observation time approach using backward implications , 1997, DAC.

[6]  Bernd Becker,et al.  Symbolic Fault Simulation for Sequential Circuits and the Multiple Observation Time Test Strategy , 1995, 32nd Design Automation Conference.

[7]  Gianpiero Cabodi,et al.  Full symbolic ATPG for large circuits , 1994, Proceedings., International Test Conference.

[8]  Miron Abramovici,et al.  Sequentially untestable faults identified without search ("simple implications beat exhaustive search!") , 1994, Proceedings., International Test Conference.

[9]  D. G. Saab,et al.  Partial reset: An inexpensive design for testability approach , 1993, 1993 European Conference on Design Automation with the European Event in ASIC Design.

[10]  Edward A. Feigenbaum,et al.  Switching and Finite Automata Theory: Computer Science Series , 1990 .

[11]  Melvin A. Breuer,et al.  On Redundancy and Fault Detection in Sequential Circuits , 1979, IEEE Transactions on Computers.

[12]  Irith Pomeranz,et al.  The Multiple Observation Time Test Strategy , 1992, IEEE Trans. Computers.

[13]  Bernd Becker,et al.  On the (non-)resetability of synchronous sequential circuits , 1996, Proceedings of 14th VLSI Test Symposium.

[14]  Irith Pomeranz,et al.  On the Role of Hardware Reset in Synchronous Sequential Circuit Test Generation , 1994, IEEE Trans. Computers.

[15]  Rolf Drechsler,et al.  Combining GAs and symbolic methods for high quality tests of sequential circuits , 1999, Proceedings of the ASP-DAC '99 Asia and South Pacific Design Automation Conference 1999 (Cat. No.99EX198).

[16]  Paolo Prinetto,et al.  Advanced techniques for GA-based sequential ATPGs , 1996, Proceedings ED&TC European Design and Test Conference.

[17]  Alexander Miczo,et al.  The Sequential ATPG: A Theoretical Limit , 1983, International Test Conference.

[18]  Daniel G. Saab,et al.  On the initialization of sequential circuits , 1994, Proceedings., International Test Conference.

[19]  Fabio Somenzi,et al.  Redundancy identification/removal and test generation for sequential circuits using implicit state enumeration , 1993, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[20]  Randal E. Bryant,et al.  Graph-Based Algorithms for Boolean Function Manipulation , 1986, IEEE Transactions on Computers.

[21]  Bernd Becker,et al.  A hybrid fault simulator for synchronous sequential circuits , 1994, Proceedings., International Test Conference.

[22]  Janak H. Patel,et al.  HITEC: a test generation package for sequential circuits , 1991, Proceedings of the European Conference on Design Automation..

[23]  Michael S. Hsiao,et al.  Sequential circuit test generation using dynamic state traversal , 1997, Proceedings European Design and Test Conference. ED & TC 97.

[24]  B. Becker,et al.  FAST-SC: Fast Fault Simulation in Synchronous Sequential circuits , 1993, The Sixth International Conference on VLSI Design.

[25]  I. Pomeranz,et al.  Fault simulation for synchronous sequential circuits under the multiple observation time testing approach , 1993, Proceedings ETC 93 Third European Test Conference.

[26]  Janak H. Patel,et al.  Accurate logic simulation in the presence of unknowns , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[27]  Vishwani D. Agrawal,et al.  STATE ASSIGNMENT FOR INITIALIZABLE SYNTHESIS , 1989 .

[28]  Nikolaus Gouders,et al.  PARIS: a parallel pattern fault simulator for synchronous sequential circuits , 1991, 1991 IEEE International Conference on Computer-Aided Design Digest of Technical Papers.

[29]  Dong Sam Ha,et al.  HOPE: an efficient parallel fault simulator for synchronous sequential circuits , 1992, DAC '92.

[30]  Seh-Woong Jeong,et al.  Synchronizing sequences and symbolic traversal techniques in test generation , 1993, J. Electron. Test..