Characteristics of Gate-All-Around Hetero-Gate-Dielectric Tunneling Field-Effect Transistors

In this paper, gate-all-around (GAA) tunneling field-effect transistors (TFETs) with hetero-gate dielectric (HG) materials have been simulated and their characteristics have been optimized as a function of the high-k dielectric length (Lhighk). For the optimization of Lhighk, simulation results have been analyzed in terms of on- and off-current (Ion, Ioff), subthreshold swing (SS), on/off current ratio, intrinsic delay time (τ), and RF performances. In the device simulations, the on-current characteristics were optimized when Lhighk is 8 nm. The optimized GAA HG TFET had ~100 times higher Ion and ~2 times improved SS than a GAA SiO2-only TFET. It has also been shown that the RF performances of TFETs can be improved by introducing an HG structure.

[1]  K. Boucart,et al.  Length scaling of the Double Gate Tunnel FET with a high-K gate dielectric , 2007 .

[2]  J.C.S. Woo,et al.  The Tunnel Source (PNPN) n-MOSFET: A Novel High Performance Transistor , 2008, IEEE Transactions on Electron Devices.

[3]  Yue Yang,et al.  Tunneling Field-Effect Transistor: Capacitance Components and Modeling , 2010, IEEE Electron Device Letters.

[4]  D. Antoniadis,et al.  Design of Tunneling Field-Effect Transistors Using Strained-Silicon/Strained-Germanium Type-II Staggered Heterojunctions , 2008, IEEE Electron Device Letters.

[5]  I. Eisele,et al.  Performance Enhancement of Vertical Tunnel Field-Effect Transistor with SiGe in the δp+ Layer , 2004 .

[6]  Byung-Gook Park,et al.  Simulation of Gate-All-Around Tunnel Field-Effect Transistor with an n-Doped Layer , 2010, IEICE Trans. Electron..

[7]  S. Datta,et al.  Effective Capacitance and Drive Current for Tunnel FET (TFET) CV/I Estimation , 2009, IEEE Transactions on Electron Devices.

[8]  S. Sedlmaier,et al.  Vertical tunnel field-effect transistor , 2004, IEEE Transactions on Electron Devices.

[9]  Qin Zhang,et al.  Low-subthreshold-swing tunnel transistors , 2006, IEEE Electron Device Letters.

[10]  Y. Yeo,et al.  Device Design and Scalability of a Double-Gate Tunneling Field-Effect Transistor with Silicon–Germanium Source , 2008 .

[11]  W. Choi,et al.  Hetero-Gate-Dielectric Tunneling Field-Effect Transistors , 2010, IEEE Transactions on Electron Devices.

[12]  Byung-Gook Park,et al.  Tunneling Field-Effect Transistors (TFETs) With Subthreshold Swing (SS) Less Than 60 mV/dec , 2007, IEEE Electron Device Letters.

[13]  Tsu-Jae King Liu,et al.  Tunnel Field Effect Transistor With Raised Germanium Source , 2010, IEEE Electron Device Letters.

[14]  J. Woo,et al.  Effect of Pocket Doping and Annealing Schemes on the Source-Pocket Tunnel Field-Effect Transistor , 2011, IEEE Transactions on Electron Devices.

[15]  B. Streetman.  Solid state electronic devices , 1972 .

[16]  Woojun Lee,et al.  Influence of Inversion Layer on Tunneling Field-Effect Transistors , 2011, IEEE Electron Device Letters.

[17]  Min-Chul Sun,et al.  Design Optimization of a Type-I Heterojunction Tunneling Field-Effect Transistor (I-HTFET) for High Performance Logic Technology , 2011 .

[18]  J.L. Hoyt,et al.  Strained-$\hbox{Si}_{1 - x}\hbox{Ge}_{x}/\hbox{Si}$ Band-to-Band Tunneling Transistors: Impact of Tunnel-Junction Germanium Composition and Doping Concentration on Switching Behavior , 2009, IEEE Transactions on Electron Devices.

[19]  I. Eisele,et al.  P-Channel Tunnel Field-Effect Transistors down to Sub-50 nm Channel Lengths , 2006 .

[20]  I. Eisele,et al.  A simulation approach to optimize the electrical parameters of a vertical tunnel FET , 2005, IEEE Transactions on Electron Devices.

[21]  A. Seabaugh,et al.  Fully-depleted Ge interband tunnel transistor: Modeling and junction formation , 2009 .

[22]  Yee-Chia Yeo,et al.  Device physics and design of double-gate tunneling field-effect transistor by silicon film thickness optimization , 2007 .

[23]  K. Boucart,et al.  Double-Gate Tunnel FET With High-$\kappa$ Gate Dielectric , 2007, IEEE Transactions on Electron Devices.

[24]  K. Banerjee,et al.  Steep Subthreshold Slope n- and p-Type Tunnel-FET Devices for Low-Power and Energy-Efficient Digital Circuits , 2009, IEEE Transactions on Electron Devices.

[25]  Sneh Saurabh,et al.  Impact of Strain on Drain Current and Threshold Voltage of Nanoscale Double Gate Tunnel Field Effect Transistor: Theoretical Investigation and Analysis , 2009 .

[26]  N. Singh,et al.  Demonstration of Tunneling FETs Based on Highly Scalable Vertical Silicon Nanowires , 2009, IEEE Electron Device Letters.

[27]  Doris Schmitt-Landsiedel,et al.  Complementary tunneling transistor for low power application , 2004 .

[28]  Woo Young Choi.  Comparative Study of Tunneling Field-Effect Transistors and Metal–Oxide–Semiconductor Field-Effect Transistors , 2010 .

[29]  J. Appenzeller,et al.  Band-to-band tunneling in carbon nanotube field-effect transistors. , 2004, Physical review letters.

[30]  Measurement of Enhanced Gate-Controlled Band-to-Band Tunneling in Highly Strained Silicon-Germanium Diodes , 2008, IEEE Electron Device Letters.

[31]  T. Nirschl,et al.  Correction to "Revision of Tunneling Field-Effect Transistor in Standard CMOS Technologies" , 2007 .