mrFPGA: A novel FPGA architecture with memristor-based reconfiguration
暂无分享,去创建一个
[1] Yu Cao,et al. New generation of predictive technology model for sub-45nm design exploration , 2006, 7th International Symposium on Quality Electronic Design (ISQED'06).
[2] Jason Cong,et al. Power modeling and characteristics of field programmable gate arrays , 2005, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[3] Patrick Schaumont,et al. Domain-Specific Codesign for Embedded Security , 2003, Computer.
[4] D. Stewart,et al. The missing memristor found , 2008, Nature.
[5] Jason Cong,et al. Customizable Domain-Specific Computing , 2009, IEEE Design & Test of Computers.
[6] André DeHon,et al. Reconfigurable architectures for general-purpose computing , 1996 .
[7] Ru Huang,et al. Resistive switching of silicon-rich-oxide featuring high compatibility with CMOS technology for 3D stackable and embedded applications , 2011 .
[8] Wei Wang,et al. 3-D nFPGA: A Reconfigurable Architecture for 3-D CMOS/Nanomaterial Hybrid Digital Circuits , 2007, IEEE Transactions on Circuits and Systems I: Regular Papers.
[9] Jonathan Rose,et al. Measuring the Gap Between FPGAs and ASICs , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[10] Fabien Clermidy,et al. Interconnection scheme and associated mapping method of reconfigurable cell matrices based on nanoscale devices , 2009, 2009 IEEE/ACM International Symposium on Nanoscale Architectures.
[11] Meng-Fan Chang,et al. Three-dimensional 4F2 ReRAM cell with CMOS logic compatible process , 2010, 2010 International Electron Devices Meeting.
[12] Wei Wang,et al. rFGA: CMOS-nano hybrid FPGA using RRAM components , 2008, 2008 IEEE International Symposium on Nanoscale Architectures.
[13] Frederick T. Chen,et al. Highly scalable hafnium oxide memory with improvements of resistive distribution and read disturb immunity , 2009, 2009 IEEE International Electron Devices Meeting (IEDM).
[14] Guy Lemieux,et al. Circuit design of routing switches , 2002, FPGA '02.
[15] Fabien Clermidy,et al. Emerging memory technologies for reconfigurable routing in FPGA architecture , 2010, 2010 17th IEEE International Conference on Electronics, Circuits and Systems.
[16] H.-S. Philip Wong,et al. Efficient FPGAs using nanoelectromechanical relays , 2010, FPGA '10.
[17] Low Energy Field-Programmable Gate Array , .
[18] Jonathan Rose,et al. The effect of LUT and cluster size on deep-submicron FPGA performance and density , 2004 .
[19] Mohammad Mahvash,et al. A memristor SPICE model for designing memristor circuits , 2010, 2010 53rd IEEE International Midwest Symposium on Circuits and Systems.
[20] Shimeng Yu,et al. Read/write schemes analysis for novel complementary resistive switches in passive crossbar memory arrays. , 2010, Nanotechnology.
[21] D. Strukov,et al. CMOL FPGA: a reconfigurable architecture for hybrid digital circuits with two-terminal nanodevices , 2005 .
[22] RoseJonathan,et al. The effect of LUT and cluster size on deep-submicron FPGA performance and density , 2004 .
[23] Vaughn Betz,et al. Architecture and CAD for Deep-Submicron FPGAS , 1999, The Springer International Series in Engineering and Computer Science.
[24] L.P.P.P. van Ginneken,et al. Buffer placement in distributed RC-tree networks for minimal Elmore delay , 1990 .
[25] Jonathan Rose,et al. Area and delay trade-offs in the circuit and architecture design of FPGAs , 2008, FPGA '08.
[26] Yuan Xie,et al. 3D-NonFAR: Three-dimensional non-volatile FPGA architecture using phase change memory , 2010, 2010 ACM/IEEE International Symposium on Low-Power Electronics and Design (ISLPED).
[27] Mingjie Lin,et al. Performance Benefits of Monolithically Stacked 3-D FPGA , 2006, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.
[28] Cong Xu,et al. Design implications of memristor-based RRAM cross-point structures , 2011, 2011 Design, Automation & Test in Europe.
[29] Heng-Yuan Lee,et al. A 5ns fast write multi-level non-volatile 1 K bits RRAM memory with advance write scheme , 2009, 2009 Symposium on VLSI Circuits.
[30] Jonathan Rose,et al. Measuring the Gap Between FPGAs and ASICs , 2007, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[31] K. Tsunoda,et al. Low Power and High Speed Switching of Ti-doped NiO ReRAM under the Unipolar Voltage Source of less than 3 V , 2007, 2007 IEEE International Electron Devices Meeting.