A NovelLow-PowerPhysical Design Methodology forMTCMOS

Theoptimization ofvirtual supply network plays an parasitic effects ofvirtual networks willimpactthecircuit important roleinMTCMOS lowpowerdesign. Existing low performance. Meanwhile, Ifnotconsidering theoptimization of powerworksaremainly ongate-level without anyoptimizationvirtual supply networks, twogateslocated farapartwillbe onphysical design level, whichcanleadtolarge amountof clustered together whichwillaugment therouting complexity of virtual supply networks. Thispaperpresents (1)alowpower thecircuit. Therefore, virtual supply network minimization plays an driven physical design flow; (2)anovel lowpowerplacement to important role inensuring MTCMOS performance aswellaslow simultaneously place standard cells andsleep transistors and(3) powerdesign requirement. sleeptransistor relocation technique tofurther reducethe InMTCMOS lowpowerdesign, theexisting worksaremainly virtual supply networks. Experiment results arepromising for twoindependent processes. Oneisthesleep transistor sizing and bothachieving up to28.15%savings forvirtual supply gateclustering ingate-level design; another isfixed-row based networks andwellcontrolling theincrease ofsignal nets. sleep transistor placement inpostlayout design.