A low-power 4-b 2.5 Gsample/s pipelined flash analog-to-digital converter using differential comparator and DCVSPG encoder

This paper presents a 4-bit high-speed, low-power, pipelined flash analog-to-digital converter (ADC). The proposed ADC is pipelined and mainly consists of three stages: 1) track-and-hold (T/H), 2) differential comparator, and 3) differential cascode voltage switch with pass gates (DCVSPG) encoder. The T/H uses a current mode, dual-array structure to reduce the aperture jitter for high input frequency. The differential comparator eliminates the use of a resistor ladder circuit by generating the reference voltages internally. The DCVSPG encoder has a full output signal swing and compact logic design style of pass gate circuits which makes it suitable for high sampling frequency. The DCVSPG encoder reduces the power consumption by a factor of 88% as compared to the conventional ROM encoder. The ADC is designed in 130 nm CMOS technology. FFT tests prove proper operation of the ADC sampled at 2.5 GHz for an input signal frequency up to 1 GHz.

[1]  Xicheng Jiang,et al.  A 2 GS/s 6 b ADC in 0.18 /spl mu/m CMOS , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..

[2]  Chien-In Henry Chen,et al.  Design Synthesis and Performance Measurement of Pipelined Flash ADC for SoC Applications , 2005, 2005 IEEE Instrumentationand Measurement Technology Conference Proceedings.

[3]  Kyusun Choi,et al.  Comparator Generation and Selection for Highly Linear CMOS Flash Analog-to-Digital Converter , 2003 .

[4]  Wei Hwang,et al.  Design and implementation of differential cascode voltage switch with pass-gate (DCVSPG) logic for high-performance digital systems , 1997 .

[5]  A. Abidi,et al.  A 6 b 1.3 GSample/s A/D converter in 0.35 /spl mu/m CMOS , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[6]  Kyusun Choi,et al.  Fat tree encoder design for ultra-high speed flash A/D converters , 2002, The 2002 45th Midwest Symposium on Circuits and Systems, 2002. MWSCAS-2002..

[7]  M. Vertregt,et al.  A 6b 1.6 Gsample/s flash ADC in 0.18 /spl mu/m CMOS using averaging termination , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[8]  Kyusun Choi,et al.  Quantum Voltage comparator for 0.07 /spl mu/m CMOS flash A/D converters , 2003, IEEE Computer Society Annual Symposium on VLSI, 2003. Proceedings..

[9]  Asad A. Abidi,et al.  A 6 b 1.3 GSample/s A/D converter in 0.35 μm CMOS , 2001 .

[10]  M. Vertregt,et al.  A 6b 1.6 Gsample/s flash ADC in 0.18 μm CMOS using averaging termination , 2002 .