Voltage Noise in Multi-Core Processors: Empirical Characterization and Optimization Opportunities

Voltage noise characterization is an essential aspect of optimizing the shipped voltage of high-end processor based systems. Voltage noise, i.e. Variations in the supply voltage due to transient fluctuations on current, can negatively affect the robustness of the design if it is not properly characterized. Modeling and estimation of voltage noise in a pre-silicon setting is typically inadequate because it is difficult to model the chip/system packaging and power distribution network (PDN) parameters very precisely. Therefore, a systematic, direct measurement-based characterization of voltage noise in a post-silicon setting is mandatory in validating the robustness of the design. In this paper, we present a direct measurement-based voltage noise characterization of a state-of-the-art mainframe class multicoreprocessor. We develop a systematic methodology to generate noise stress marks. We study the sensitivity of noise in relation to the different parameters involved in noise generation: (a) stimulus sequence frequency, (b) supply current delta, (c) number of noise events and, (d) degree of alignment or synchronization of events in a multi-core context. By sensing per-core noise in a multi-core chip, we characterize the noise propagation across the cores. This insight opens up new opportunities for noise mitigation via workload mappings and dynamic voltage guard banding.

[1]  Michael D. Smith,et al.  Voltage Noise in Production Processors , 2011, IEEE Micro.

[2]  Meeta Sharma Gupta,et al.  Eliminating voltage emergencies via software-guided code transformations , 2010, TACO.

[3]  Meeta Sharma Gupta,et al.  Systematic Energy Characterization of CMP/SMT Processor Systems via Automated Micro-Benchmarks , 2012, 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture.

[4]  Margaret Martonosi,et al.  Control techniques to eliminate voltage emergencies in high performance processors , 2003, The Ninth International Symposium on High-Performance Computer Architecture, 2003. HPCA-9 2003. Proceedings..

[5]  T. N. Vijaykumar,et al.  Exploiting resonant behavior to reduce inductive noise , 2004, Proceedings. 31st Annual International Symposium on Computer Architecture, 2004..

[6]  Lizy Kurian John,et al.  Performance boosting under reliability and power constraints , 2013, 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[7]  Shohaib Aboobacker.  RAZOR: circuit-level correction of timing errors for low-power operation , 2011 .

[8]  D. Albonesi,et al.  Mitigating inductive noise in SMT processors , 2004, Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758).

[9]  Trevor Mudge,et al.  Razor: a low-power pipeline based on circuit-level timing speculation , 2003, Proceedings. 36th Annual IEEE/ACM International Symposium on Microarchitecture, 2003. MICRO-36..

[10]  George A. Katopis,et al.  Mid-frequency simultaneous switching noise in computer systems , 1997, 1997 Proceedings 47th Electronic Components and Technology Conference.

[11]  Gu-Yeon Wei,et al.  Characterizing and evaluating voltage noise in multi-core near-threshold processors , 2013, International Symposium on Low Power Electronics and Design (ISLPED).

[12]  Larry D. Smith,et al.  Power distribution system design methodology and capacitor selection for modern CMOS technology , 1999 .

[13]  Samuel Naffziger,et al.  5.6 Adaptive clocking system for improved power efficiency in a 28nm x86-64 microprocessor , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

[14]  Radu Teodorescu,et al.  Dynamic reduction of voltage margins by leveraging on-chip ECC in Itanium II processors , 2013, ISCA.

[15]  Xiang Pan,et al.  VRSync: Characterizing and eliminating synchronization-induced voltage emergencies in many-core processors , 2012, 2012 39th Annual International Symposium on Computer Architecture (ISCA).

[16]  Eli Chiprout,et al.  A microarchitecture-based framework for pre- and post-silicon power delivery analysis , 2009, 2009 42nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[17]  Wei Huang,et al.  Some Limits of Power Delivery in the Multicore Era , 2012 .

[18]  Jaydeep P. Kulkarni,et al.  5.7 A graphics execution core in 22nm CMOS featuring adaptive clocking, selective boosting and state-retentive sleep , 2014, 2014 IEEE International Solid-State Circuits Conference Digest of Technical Papers (ISSCC).

[19]  Brooks David,et al.  Voltage Noise: Why It’s Bad, and What To Do About It , 2009 .

[20]  Bishop Brock,et al.  Introducing the Adaptive Energy Management Features of the Power7 Chip , 2011, IEEE Micro.

[21]  David M. Brooks,et al.  Eliminating voltage emergencies via microarchitectural voltage control feedback and dynamic optimization , 2004, Proceedings of the 2004 International Symposium on Low Power Electronics and Design (IEEE Cat. No.04TH8758).

[22]  Lizy Kurian John,et al.  AUDIT: Stress Testing the Automatic Way , 2012, 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture.

[23]  G.A. Katopis,et al.  Delta-I noise specification for a high-performance computing machine , 1985, Proceedings of the IEEE.

[24]  Meeta Sharma Gupta,et al.  DeCoR: A Delayed Commit and Rollback mechanism for handling inductive noise in processors , 2008, 2008 IEEE 14th International Symposium on High Performance Computer Architecture.

[25]  Kevin Skadron,et al.  Architecture implications of pads as a scarce resource , 2014, 2014 ACM/IEEE 41st International Symposium on Computer Architecture (ISCA).

[26]  Chung-Lung Kevin Shum,et al.  Circuit and Physical Design of the zEnterprise™ EC12 Microprocessor Chips and Multi-Chip Module , 2014, IEEE Journal of Solid-State Circuits.

[27]  Vivek Tiwari,et al.  An architectural solution for the inductive noise problem due to clock-gating , 1999, Proceedings. 1999 International Symposium on Low Power Electronics and Design (Cat. No.99TH8477).

[28]  George A. Katopis,et al.  Decoupling capacitor effects on switching noise , 1992, [1992 Proceedings] Electrical Performance of Electronic Packaging.

[29]  Charles F. Webb.  IBM z10: The Next-Generation Mainframe Microprocessor , 2008, IEEE Micro.

[30]  Vivek Tiwari,et al.  Inductive noise reduction at the architectural level , 2000, VLSI Design 2000. Wireless and Digital Imaging in the Millennium. Proceedings of 13th International Conference on VLSI Design.

[31]  Meeta Sharma Gupta,et al.  Understanding Voltage Variations in Chip Multiprocessors using a Distributed Power-Delivery Network , 2007, 2007 Design, Automation & Test in Europe Conference & Exhibition.

[32]  Shen Lin,et al.  Ramp Up/Down Functional Unit to Reduce Step Power , 2000, PACS.

[33]  P.J. Restle,et al.  Timing uncertainty measurements on the Power5 microprocessor , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[34]  Keith A. Bowman,et al.  A 22nm dynamically adaptive clock distribution for voltage droop tolerance , 2012, 2012 Symposium on VLSI Circuits (VLSIC).

[35]  Meeta Sharma Gupta,et al.  Voltage emergency prediction: Using signatures to reduce operating margins , 2009, 2009 IEEE 15th International Symposium on High Performance Computer Architecture.

[36]  Margaret Martonosi,et al.  Wavelet analysis for microprocessor design: experiences with wavelet-based dI/dt characterization , 2004, 10th International Symposium on High Performance Computer Architecture (HPCA'04).

[37]  T. N. Vijaykumar,et al.  Pipeline muffling and a priori current ramping: architectural techniques to reduce high-frequency inductive noise , 2003, ISLPED '03.

[38]  John L. Prince,et al.  Simultaneous Switching Noise of CMOS Devices and Systems , 1993 .

[39]  William V. Huott,et al.  On-chip Timing Uncertainty Measurements on IBM Microprocessors , 2008, 2008 IEEE International Test Conference.

[40]  Lizy Kurian John,et al.  Automated di/dt stressmark generation for microprocessor power delivery networks , 2011, IEEE/ACM International Symposium on Low Power Electronics and Design.

[41]  Wiren D. Becker,et al.  Modeling, measurement, and simulation of simultaneous switching noise , 1996 .

[42]  Wiren D. Becker,et al.  Mid-frequency delta-I noise analysis of complex computer system boards with multiprocessor modules and verification by measurements , 2001 .

[43]  Srinivas Nimmagadda.  Simultaneous switching noise and its impact on CMOS digital systems , 1992 .

[44]  William V. Huott,et al.  Comparison of Split-Versus Connected-Core Supplies in the POWER6 Microprocessor , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[45]  Mark C. Toburen.  Power analysis and instruction scheduling for reduced di/dt in the execution core of high-performanc , 1999 .

[46]  Kevin Skadron,et al.  Walking pads: Fast power-supply pad-placement optimization , 2014, 2014 19th Asia and South Pacific Design Automation Conference (ASP-DAC).

[47]  Bishop Brock,et al.  Active management of timing guardband to save energy in POWER7 , 2011, 2011 44th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO).

[48]  Michael D. Smith,et al.  Voltage Smoothing: Characterizing and Mitigating Voltage Noise in Production Processors via Software-Guided Thread Scheduling , 2010, 2010 43rd Annual IEEE/ACM International Symposium on Microarchitecture.

[49]  Fadi Busaba,et al.  IBM zEC12: The Third-Generation High-Frequency Mainframe Microprocessor , 2013, IEEE Micro.

[50]  Timothy J. Slegel,et al.  IBM's S/390 G5 microprocessor design , 1999, IEEE Micro.

[51]  B. Beker,et al.  Modeling of power distribution systems for high-performance microprocessors , 1999 .

[52]  Bishop Brock,et al.  Adaptive energy-management features of the IBM POWER7 chip , 2011, IBM J. Res. Dev..

[53]  Meeta Sharma Gupta,et al.  Towards a software approach to mitigate voltage emergencies , 2007, Proceedings of the 2007 international symposium on Low power electronics and design (ISLPED '07).

[54]  Sanjay Pant,et al.  Power Grid Physics and Implications for CAD , 2007, IEEE Design & Test of Computers.